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參數(shù)資料
| 型號： | S2102 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Fibre Channel Device(光纖通道雙收發(fā)器) |
| 中文描述： | 雙光纖通道設(shè)備（光纖通道雙收發(fā)器） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 294K |
| 代理商： | S2102 |
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6
DUAL FIBRE CHANNEL DEVICE
S2102
October 6, 2000 / Revision C
Table 3. Operating Rates
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rate, regardless of whether the reference is provided
at 1/10 or 1/20 the serial data rate. This clock can be
buffered as required without concern about added
delay. There is no phase requirement between
TCLKO and TBCx, which is provided back to the
S2102, other than that they remain within
±
3ns of
the phase relationship established at reset.
The S2102 also supports the traditional REFCLK
clocking found in many Fibre Channel applications
and is illustrated in Figure 6.
Half Rate Operation
The S2102 supports full and half rate operation for
all modes of operation. When RATE is LOW, the
S2102 serial data rate equals the VCO frequency.
When RATE is HIGH, the VCO is divided by 2 before
being provided to the chip. Thus the S2102 can sup-
port Fibre Channel and serial backplane functions at
both full and half the VCO rate. See Table 3.
Parallel to Serial Conversion
The 10-bit parallel data handled by the S2102 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with ANSI X3.230 FC-PH (Fibre Chan-
nel Physical and Signaling Interface).
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data
1
.
Table 2 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2102. The S2102 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2102 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2102 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to ensure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL=1. In both cases the fre-
quency of the parallel word rate output, TCLKO, is
constant at 1/10 the serial data rate. See Table 3.
Serial Data Outputs
The S2102 provides LVPECL level serial outputs.
The serial outputs do not require output pulldown
resistors. Outputs are designed to perform optimally
when AC-coupled.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. TCLKO will oper-
ate normally regardless of the state of RESET.
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
Table 2. Data to 8B/10B Alphabetic Representation
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