參數(shù)資料
型號(hào)： S2102
廠商： Applied Micro Circuits Corp.
英文描述： Dual Fibre Channel Device(光纖通道雙收發(fā)器)
中文描述： 雙光纖通道設(shè)備（光纖通道雙收發(fā)器）
文件頁(yè)數(shù)： 1/28頁(yè)
文件大?。?/td> 294K
代理商： S2102
1
S2102
S2102
DUAL FIBRE CHANNEL DEVICE
October 6, 2000 / Revision C
DEVICE
SPECIFICATION
MAC
(ASIC)
S2002
DUAL
FIBRE
CHANNEL
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2102
FC INTERFACE
SERIAL BP DRIVER
Figure 1. Typical Dual Fibre Channel Application
FEATURES
1062 MHz (Fibre Channel) operating rate
- Half rate operation
Dual Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
ANSI x3T11 Fibre Channel Compatible
Dual Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.85 W power dissipation
Compact 21mm x 21mm 156 TBGA package
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2102 facilitates high-speed serial transmission
of data in a variety of applications including Fibre
Channel, serial backplanes, and proprietary point to
point links. The chip provides two separate trans-
ceivers which are operated individually for a data
capacity of >2 Gbps.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation/
recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip dual receive PLL is used for
clock recovery and data re-timing on the two inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces with ex-
cellent signal integrity. Local loopback mode allows
for system diagnostics. The chip requires a 3.3V
power supply and dissipates 1.85 watts.
Figure 1 shows the S2102 and S2002 in a Fibre
Channel application. Figure 2 summarizes the in-
put/output signals of the device. Figures 3 and 4
show the transmit and receive block diagrams, re-
spectively.
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