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參數(shù)資料
| 型號(hào)： | S2102 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Fibre Channel Device(光纖通道雙收發(fā)器) |
| 中文描述： | 雙光纖通道設(shè)備（光纖通道雙收發(fā)器） |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 294K |
| 代理商： | S2102 |
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7
S2102
DUAL FIBRE CHANNEL DEVICE
October 6, 2000 / Revision C
RECEIVER DESCRIPTION
Each receiver channel is designed to implement a
Serial Backplane receiver function through the physi-
cal layer. A block diagram showing the basic func-
tion is provided in Figure 4.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2102 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2102. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for each channel is enabled by its respective LPEN
input.
The high speed serial inputs to the S2102 are inter-
nally biased to VDD-1.3V. All that is required exter-
nally are AC-coupling and line-to-line differential
termination.
Clock Recovery Function
Clock recovery is performed on the input data
stream for each channel of the S2102. The receiver
PLL has been optimized for the anticipated needs of
Serial Backplane systems. A simple state machine in
the clock recovery macro decides whether to acquire
lock from the serial data input or from the reference
clock. The decision is based upon the frequency and
run length of the serial data inputs. If at any time the
frequency or run length checks are violated, the
state machine forces the VCO to lock to the refer-
ence clock. This allows the VCO to maintain the cor-
rect frequency in the absence of data.
The “l(fā)ock to reference” frequency criteria ensure that
the S2102 will respond to variations in the serial data
input frequency (compared to the reference fre-
quency). The new lock state is dependent upon the
current lock state, as shown in Table 4.
The run-length criteria ensure that the S2102 will
respond appropriately and quickly to a loss of signal.
The run-length checker flags a condition of consecu-
tive ones or zeros across 12 parallel words. Thus
119 or less consecutive ones or zeros does not
cause signal loss, 129 or more causes signal loss,
and 120 - 128 may or may not, depending on how
the data aligns across byte boundaries.
If both the off-frequency detect circuitry test and the
run-length test are satisfied, the CRU will attempt to
lock to the incoming data. It is possible for the run
length test to be satisfied due to noise on the inputs,
even if no signal is present. In this case the receiver
VCO will maintain frequency accuracy to within 100
ppm of the target rate as determined by REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
Reference Clock Input
A single reference clock, which serves both transmit-
ter and receiver, must be provided from a low jitter
clock source. The frequency of the received data
stream (divided-by-10 or -20) must be within 200
ppm of the reference clock to ensure reliable locking
of the receiver PLL.
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Table 4. Lock to Reference Frequency Criteria
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