參數資料
型號: S2075
廠商: Applied Micro Circuits Corp.
英文描述: Fibre Channel Bit Stream Monitor with Repeater(帶中繼器的光纖位流監(jiān)視器)
中文描述: 光纖通道比特流監(jiān)視器與中繼器(帶中繼器的光纖位流監(jiān)視器)
文件頁數: 3/21頁
文件大小: 168K
代理商: S2075
3
S2075
FIBRE CHANNEL BIT STREAM MONITOR WITH REPEATER
May 15, 2000 / Revision A
S2075 OVERVIEW
The S2075 provides repeater serialization and
deserialization functions for block encoded data to
implement a Fibre Channel interface. The S2075
functional block diagram is depicted in Figure 2.
The device operates in two basic modes, controlled
by the PBCSEL input, as shown in Table 1. In moni-
tor mode, the parallel input is unused, the device
functions as a repeater with parallel output monitor
capability. In transceiver mode, the device functions
as a fibre channel transceiver. The sequence of op-
eration for each mode is as follows:
Monitor Mode
1.
Serial Input
2.
Clock and data recovery
3a. Serial output
3b. Serial-to-parallel conversion, frame detection,
and 10-bit parallel output.
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5
6
7
8
9
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Table 2. Data Mapping to 8B/10B
Alphabetic Representation
1
A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC 9391, May 1982.
Table 1. Operating Modes
S
C
B
P
Transceiver Mode
Transmitter
1.
10-bit parallel input
2.
Parallel-to-serial conversion
3.
Serial output
Receiver
1.
Clock and data recoverery from serial input
2.
Serial-to-parallel conversion
3.
Frame detection
4.
10-bit parallel output
The 10-bit parallel data input to the S2075 should be
from a DC-balanced encoding scheme, such as the
8B/10B transmission code, in which information to be
transmitted is encoded 8 bits at a time into 10-bit trans-
mission characters
1
. For reference, Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
Loop Back
Local loopback provides a capability for performing
off-line testing. This is useful for ensuring the integ-
rity of the serial channel before enabling the trans-
mission medium. It also allows for system
diagnostics.
Repeater
1. Fully differential for minimum deterministic jitter
accumulation (10 ps nominal).
2. High speed LVPECL I/O.
L
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D
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