參數(shù)資料
型號: S2009
廠商: Applied Micro Circuits Corp.
英文描述: 1.6 Gbps Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的1.6 Gbps四串行收發(fā)器)
中文描述: 1.6 Gbps的四串行背板設(shè)備(用于高速串行數(shù)據(jù)傳送的1.6 Gbps的四串行收發(fā)器)
文件頁數(shù): 9/42頁
文件大?。?/td> 1866K
代理商: S2009
9
S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
February 9, 2001 / Revision C
Table 4. Data to 8B/10B Alphabetic Representation
e
B
a
D
]
U
O
D
r
]
N
I
D
0
1
2
3
4
5
6
7
8
9
B
0
1
B
8
n
o
e
s
e
e
R
c
m
u
n
a
h
p
a
b
c
d
e
i
f
g
h
j
Table 5. Operating Rates
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within
±
100 ppm of each other to en-
sure that the clock recovery units can lock to the
serial data.
The frequency of the reference clock is 1/20 the se-
rial data rate. The frequency of the parallel word rate
output, TCLKO, is constant at 1/10 the serial data
rate, while the TCLKO2 output is constant at 1/20
the serial data rate. See Table 5.
Serial Data Outputs
The S2009 provides LVPECL level serial outputs.
The serial ouputs do not require output pulldown re-
sistors. Outputs are designed to perform optimally
when AC-coupled.
When operating in the Channel Lock Mode, the user
must insure that the path length of the four high speed
serial data signals are matched to within 50 bit times
of delay. Failure to meet this requirement may result
in bit errors in the received data or in byte misalign-
ment.
In addition to path length induced timing skew, the
S2009 can tolerate up to
±
3 ns of phase drift be-
tween channels after deskewing the outputs.
Test Functions
The S2009 can be configured for factory test to aid
in functional testing of the device. When in the test
mode, the internal transmit and receive Voltage Con-
trolled Oscillator (VCO) is bypassed and the refer-
ence clock substituted. This allows full functional
testing of the digital portion of the chip or bypassing
the internal synthesized clock with an external clock
source. (See Other Operating Modes section.)
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TCLK to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET_N signal. The transmit
FIFO is also reset when the special synchronization
pattern (SYNC=1, DN=1) is generated. TCLKO and
TCLKO2 will operate normally regardless of the state
of RESET_N.
K
c
L
n
C
e
u
F
E
q
e
R
r
y
F
l
e
t
u
p
S
t
e
R
u
O
O
n
K
e
L
u
C
q
T
e
r
y
c
F
2
c
O
n
K
e
u
L
C
e
T
r
y
q
F
0
2
R
D
S
z
H
G
6
0
1
R
D
S
0
2
R
D
S
Note: SDR = Serial Data Rate.
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