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參數(shù)資料
| 型號(hào)： | S2009 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | 1.6 Gbps Quad Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的1.6 Gbps四串行收發(fā)器) |
| 中文描述： | 1.6 Gbps的四串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的1.6 Gbps的四串行收發(fā)器） |
| 文件頁(yè)數(shù)： | 8/42頁(yè) |
| 文件大小： | 1866K |
| 代理商： | S2009 |
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8
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
S2009
February 9, 2001 / Revision C
Table 3. K Character Generation (DNx = 1 KGENx =1 SYNC = 0)
K
a
r
r
e
a
h
C
]
N
I
D
N
E
G
K
+
D
R
t
n
e
r
u
C
-
D
R
t
n
e
r
u
C
s
n
e
m
m
o
C
j
g
f
i
d
c
b
a
j
g
f
i
d
c
b
a
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
7
2
7
2
7
2
7
3
K
K
K
K
K
K
K
K
K
K
K
K
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
r
a
h
C
c
n
y
S
In order to provide interface compatibility to non-
AMCC serial backplane transceivers, the S2009 can
also generate a unique sync character consisting of
16 consecutive K28.5 characters. This event is initi-
ated by the simultaneous assertion of SYNC and
DN. The SYNC character may start with either a
positive or negative parity K28.5. (Depending on the
current running disparity.) The parity of the second
and third K28.5 are inverse with respect to a valid
8B/10B sequence. Parity of the remaining K28.5 are
8B/10B compliant. Thus the parity of the K28.5 pat-
tern consists of + + - - + - + - + - + - + - + - or - - + + -
+ - + - + - + - + - +.
When operating in the Channel Lock Mode, the
KGENx and DNx inputs must be driven for each
channel. The SYNC input is common to all four
channels. Table 2 identifies the S2009 transmit con-
trol signals.
C
N
Y
S
x
N
E
G
K
x
N
D
t
u
p
t
u
O
9
0
0
2
S
0
0
0
.
D
l
P
d
e
d
o
c
n
E
0
0
1
.
a
h
C
5
2
K
0
1
1
d
n
a
3
e
a
T
y
b
d
e
n
d
s
a
r
a
h
.
N
C
I
K
D
1
X
1
d
e
n
e
g
r
.
a
h
F
c
C
t
N
m
s
Y
n
S
d
w
e
h
6
1
l
e
e
d
p
n
S
a
O
a
s
s
The special SYNC generation commences on the first
cycle in which SYNC and DN=1 and continues for 16
cycles. During this period, the SYNC, KGEN, and DN
inputs are ignored (assertion of DN and SYNC during
this period will not prolong or re-initialize the special
sync character generation).
Frequency Synthesizer (PLL)
The S2009 synthesizes a serial transmit clock from
the reference signal. Upon startup, the S2009 will
obtain phase and frequency lock within 2500 bit
times after the start of receiving reference clock in-
puts. Reliable locking of the transmit PLL is assured,
but a lock-detect output is NOT provided.
Table 2. Transmitter Control Signals
Note: ‘010’, ‘100’, and ‘110’ are reserved states.
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