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參數(shù)資料
| 型號： | S2002 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器) |
| 中文描述： | 雙串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器） |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 311K |
| 代理商： | S2002 |
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6
DUAL SERIAL BACKPLANE DEVICE
S2002
October 9, 2000 / Revision B
TRANSMITTER DESCRIPTION
The transmitter section of the S2002 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Two channels are
provided with a variety of options regarding input
clocking and loopback. The transmitters can operate
in the range of .98 GHz to 1.3 GHz, 10 or 20 times
the reference clock frequency.
Data Input
The S2002 has been designed to simplify the paral-
lel interface data transfer and provides the utmost in
flexibility regarding clocking of parallel data. The
S2002 incorporates a unique FIFO structure on both
the parallel inputs and the parallel outputs which en-
ables the user to provide a “clean” reference source
for the PLL and to accept a separate external clock
which is used exclusively to reliably clock data into
the device. Data can also be clocked in using the
REFCLK.
Data is input to each channel of the S2002 nominally
as a 10 bit wide word. This consists of eight data bits
of user data, KGEN, and DN. An input FIFO and a
clock input, TCLKx, are provided for each channel of
the S2002. The device can operate in two different
modes. The S2002 can be configured to use either
the TCLKx (TCLK MODE) input or the REFCLK input
(REFCLK MODE). In TCLK or REFCLK mode, each
byte of data is clocked into its FIFO with the TCLKx
provided for each byte. Table 1 provides a summary
of the input modes for the S2002.
Operation in the TCLK MODE makes it easier for
users to meet the relatively narrow setup and hold
time window required by the parallel 10-bit interface.
The TCLK signal is used to clock the data into an
internal holding register and the S2002 synchronizes
its internal data flow to insure stable operation. How-
ever, regardless of the clock mode, REFCLK is al-
ways the VCO reference clock. This facilitates the
provision of a clean reference clock resulting in mini-
mum jitter on the serial output. The TCLK must be
frequency locked to REFCLK, but may have an arbi-
trary phase relationship. Adjustment of internal tim-
ing of the S2002 is performed during reset. Once
synchronized, the user must insure that the timing of
the TCLK signal does not change by more than
±
3
ns relative to the REFCLK.
Figure 6 demonstrates the flexibility afforded by the
S2002. A low jitter reference is provided directly to
the S2002 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. The frequency of this output is con-
stant at the parallel word rate, 1/10 the serial data
rate, regardless of whether the reference is provided
at 1/10 or 1/20 the serial data rate. This clock can be
buffered as required without concern about added
delay. There is no phase requirement between
TCLKO and TCLKx, which is provided back to the
S2002, other than that they remain within
±
3ns of
the phase relationship established at reset.
Table 1. Input Modes
E
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T
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O
0
a
d
k
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c
.
E
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s
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C
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F
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o
1
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.
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.
c
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K
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n
s
Note that internal sychronization of FIFOs is performed upon de-
assertion of RESET or when the synchronization pattern is
generated (SYNC = 1 DNx = 1).
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