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參數(shù)資料
| 型號： | S2002 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器) |
| 中文描述： | 雙串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器） |
| 文件頁數(shù)： | 13/33頁 |
| 文件大小： | 311K |
| 代理商： | S2002 |
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13
S2002
DUAL SERIAL BACKPLANE DEVICE
October 9, 2000 / Revision B
Figure 8. S2002 Diagnostic Loopback Operation
CRU
CSU
OTHER OPERATING MODES
Operating Frequency Range
The S2002 is designed to operate at serial baud
rates of .98 GHz to 1.3 GHz (800 Mbps to 1040
Mbps user data rate). The part is specified at Fibre
Channel (1062 MHz) and Gigabit Ethernet (1.25
GHz) serial baud rates, but will operate satisfactorily
at any rate in this range.
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver, as shown in Figure 8. This provides the
ability to perform system diagnostics and off-line
testing of the interface to verify the integrity of the
serial channel. Loopback mode is enabled indepen-
dently for each channel using its respective
loopback-enable input, LPEN.
Test Modes
The RESET pin is used to initialize the Transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization).
Note: Serial output data remains active during loopback opera-
tion to enable other system tests to be performed.
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Table 8. Output Clock Mode
Table 8A. S2002 Data Clocking
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REFCLK
TCLKO
SerDes
TCLKA
REF
OSCILLATOR
Controller/MAC
ASIC/FPGA
PLL
Parallel Data
RCxP/N
2
Recovered
Clock
Figure 9. External Receiver Clocking
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