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參數(shù)資料
| 型號： | S2002 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器) |
| 中文描述： | 雙串行背板設(shè)備（用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器） |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 311K |
| 代理商： | S2002 |
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14
DUAL SERIAL BACKPLANE DEVICE
S2002
October 9, 2000 / Revision B
JTAG TESTING
The JTAG implementation for the S2002 is compli-
ant with the IEEE1149.1 requirements. JTAG is used
to test the connectivity of the pins on the chip. The
TAP, (Test Access Port), provides access to the test
logic of the chip. When TRST is asserted the TAP is
initialized. TAP is a state machine that is controlled
by TMS. The test instruction and data are loaded
through TDI on the rising edge of TCK. When TMS is
high the test instruction is loaded into the instruction
register. When TMS is low the test data is loaded
into the data register. TDO changes on the falling
edge of TCK. All input pins, including clocks, that
have boundary scan are observe only. They can be
sampled in either normal operational or test mode.
All output pins that have boundary scan, are observe
and control. They can be sampled as they are driven
out of the chip in normal operational mode, and they
can be driven out of the chip in test mode using the
Extest instruction. Since JTAG testing operates only
on digital signals there are some pins with analog
signals that JTAG does not cover. The JTAG imple-
mentation has the three required instruction, Bypass,
Extest, and Sample/Preload.
Instruction
BYPASS
EXTEST
SAMPLE/PRELOAD
ID CODE
Code
11
00
01
10
JTAG Instruction Description:
The BYPASS register contains a single shift-register
stage and is used to provide a minimum-length serial
path between the TDI and TDO pins of a component
when no test operation of that component is re-
quired. This allows more rapid movement of test
data to and from other components on a board that
are required to perform test operations.
The EXTEST instruction allows testing of off-chip cir-
cuitry and board level interconnections. Data would
typically be loaded onto the latched parallel outputs
of boundary-scan shift-register stages using the
SAMPLE/PRELOAD instruction prior to selection of
the EXTEST instruction.
The SAMPLE/PRELOAD instruction allows a snap-
shot of the normal operation of the component to be
taken and examined. It also allows data values to be
loaded onto the latched parallel outputs of the
boundary-scan shift register prior to selection of the
other boundary-scan test instructions.
The following table provides a list of the pins that are
JTAG tested. Each port has a boundary scan regis-
ter (BSR), unless otherwise noted. The following fea-
tures are described: the JTAG mode of each register
(input, output2, or internal (refers to an internal pack-
age pin)), the direction of the port if it has a bound-
ary scan register (in or out), and the position of this
register on the scan chain.
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| S2012D | SCRs (1 A to 70 A) |
| S2012D | SCRs |
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參數(shù)描述 |
|---|---|
| S200-2-00 | 功能描述:焊料和屏蔽管 2.67mm Fluoropolymer XPARENT BLUE RoHS:否 制造商:TE Connectivity / Raychem 類型:Shield Terminators 材料:Polyvinylidene Fluoride 內(nèi)徑:5.08 mm 長度:16.5 mm 最低收縮溫度: 系列:S03 |
| S200-2-00CS2904 | 制造商:TE Connectivity 功能描述:F94898N001 |
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| S200-2-01 | 制造商:TE Connectivity 功能描述:S200-2-01 |
| S200-2-01-100HN | 功能描述:焊料和屏蔽管 S200-2-01-100HN RoHS:否 制造商:TE Connectivity / Raychem 類型:Shield Terminators 材料:Polyvinylidene Fluoride 內(nèi)徑:5.08 mm 長度:16.5 mm 最低收縮溫度: 系列:S03 |
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