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參數(shù)資料
| 型號： | S2002 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Serial Backplane Device(用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器) |
| 中文描述： | 雙串行背板設備（用于高速串行數(shù)據(jù)傳送的雙串行收發(fā)器） |
| 文件頁數(shù)： | 12/33頁 |
| 文件大?。?/td> | 311K |
| 代理商： | S2002 |
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12
DUAL SERIAL BACKPLANE DEVICE
S2002
October 9, 2000 / Revision B
8B/10B Decoding
After serial to parallel conversion, the S2002 pro-
vides 8B/10B decoding of the data. The received 10-
bit codeword is decoded to recover the original 8-bit
data. The decoder also checks for errors and flags,
either invalid codeword errors or running disparity
errors by assertion of the ERRx signal. Error type is
determined by examining the EOF output in accor-
dance with Table 7. When more than one reportable
condition occurs simultaneously, reporting is in ac-
cordance with the rank assigned by Table 7.
Data Output
Data is output on the DOUT[0:7] outputs. K-characters
are flagged using the KFLAG signal. The EOF (with
KFLAG) is used to indicate the reception of a valid
K28.5 character. Invalid codewords and decoding er-
rors are indicated on the ERR output. KFLAG, EOF,
and ERR are buffered with the data in the FIFO to
insure that all outputs are synchronized at the S2002
outputs. Errors are reported independently for each
channel in TCLK or REFCLK mode operation.
The S2002 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 8. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RCxP/N
outputs. Data should be clocked on the rising edge
of RCxP. When CMODE is Low, a complementary
TTL clock at 1/2 the data rate is provided. Data
should be latched on the rising edge of RCxP and
the rising edge of RCxN.
In Fibre Channel and Gigabit Ethernet applications,
multiple consecutive K28.5 characters cannot be
generated. However, for serial backplane applica-
tions this can occur. The S2002 must be able to
operate properly when multiple K28.5 characters are
received. After the first K28.5 is detected and
aligned, the RCxP/N clock will operate without
glitches or loss of cycles.
Receiver Output Clocking
The S2002 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 8A describes the receiver output clocking op-
tions available.
When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 9. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
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