參數(shù)資料
型號(hào)： S1R72V17B00A
元件分類(lèi)： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封裝： 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件頁(yè)數(shù)： 31/45頁(yè)
文件大?。?/td> 3044K
代理商： S1R72V17B00A
6. Functional Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
17
Table 6.8 lists the control items and status relating to the transaction processing for the general-purpose
endpoints EPa, EPb, Epc, Epd and EPe.
Table 6.8 General.purpose Endpoint Control Items and Status
Item
Register/Bit
Description
Automatic ForceNAK
set
D_EPx{x=a-e}Control.AutoForceNAK
Sets the D_EPx{x=a-e}Control.ForceNAK bit for
an endpoint each time an OUT transaction at
that endpoint is completed.
Short packet transmit
enable
D_EPx{x=a-e}Control.EnShortPkt
Enables transmission of short packets less than
Max. packet size for an IN transaction. This bit is
cleared when the IN transaction that transmitted
a short packet is completed.
Automatic ForceNAK
set by short packet
reception disable
D_EPx{x=a-e}Control.
DisAF_NAK_Short
Disables the function(*) to automatically set the
D_EPx{x=a-e}Control.ForceNAK bit for an
endpoint when a short packet is received for that
endpoint in an OUT transaction.
*: This function remains enabled unless it is
disabled by this bit.
Toggle sequence bit
D_EPx{x=a-e}Control.ToggleStat
Indicates the status of the toggle sequence bit.
Toggle set
D_EPx{x=a-e}Control.ToggleSet
Sets the toggle sequence bit.
Toggle clear
D_EPx{x=a-e}Control.ToggleClr
Clears the toggle sequence bit.
Forced NAK response
D_EPx{x=a-e}Control.ForceNAK
Always responds with NAK for transactions
irrespective of the data quantity and free space
in the FIFO.
STALL response
D_EPx{x=a-e}Control.ForceSTALL
Responds with STALL for transactions.
Transaction status
D_EPx{x=a-e}IntStat.OUT_ShortACK,
D_EPx{x=a-e}IntStat.IN_TranACK,
D_EPx{x=a-e}IntStat.OUT_TranACK,
D_EPx{x=a-e}IntStat.IN_TranNAK,
D_EPx{x=a-e}IntStat.OUT_TranNAK,
D_EPx{x=a-e}IntStat.IN_TranErr,
D_EPx{x=a-e}I~tStat.OUT_TranErr
Indicates the result of a transaction.
6.2.2.1
SETUP Transactions
SETUP transactions addressed to the endpoint EP0 of the local node are unconditionally executed.
(The USB functions must be enabled by the D_NegoControl.ActiveUSB bit before this can occur.)
When a SETUP transaction is issued, the LSI stores the entire content of the data packet (8 bytes) in
the D_EP0SETUP_0 through D_EP0SETUP_7 registers and then returns an ACK response.
Furthermore, except for SetAddress() requests, the LSI issues a RcvEP0SETUP status to the
firmware.
If an error occurs during the SETUP transaction, the LSI does not respond, nor does it issue a status.
When the SETUP transaction is completed, the LSI sets the ForceNAK bit and clears the
ForceSTALL bit in the D_EP0ControlIN and D_EP0ControlOUT registers. It also sets the
ToggleStat bit. Furthermore, it sets the D_SETUP_Control.ProtectEP0 bit. When the firmware has
finished setting up the endpoint EP0 and is ready to go to the next stage, it should clear the
SETUP_Control.ProtectEP0 bit and then the ForceNAK bit in the D_EP0ControlIN or
D_EP0ControlOUT register for the direction concerned.
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