參數(shù)資料
型號(hào)： S1R72V17B00A
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封裝： 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件頁(yè)數(shù)： 15/45頁(yè)
文件大?。?/td> 3044K
代理商： S1R72V17B00A
2. Features
2
EPSON
S1R72V17*** Technical Manual (Rev.1.6)
2. Features
<< USB2.0 device functions >>
Supports HS <480 Mbps) and FS (12 Mbps) transfers.
Includes FS/HS termination (external circuit unnecessary).
Includes VBUS 5V interface (external circuit unnecessary).
Supports control, bulk, interrupt, and isochronous transfers.
Supports five general-purpose (Bulk, Interrupt, and Isochronous transfer) endpoints and Endpoint 0.
<< USB2.0 host functions >>
Supports HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) transfers.
Includes pull-down resistors for downstream ports (external circuit unnecessary).
Includes HS termination (external circuit unnecessary).
Supports control, bulk, and interrupt transfers.
Channel structure
One (1) channel used exclusively for Control transfer
Includes five general-purpose (Bulk, and Interrupt transfer) channels.
USB power switch interface.
<< CPU interface >>
Accepts 16-bit or 8-bit wide general-purpose CPU interfaces.
Incorporates one DMA channel (Multiword transfer).
Big Endian (incorporating a bus swap function for Little Endian CPUs).
Changeable interface voltages (3.3 V to 1.8 VTyp).
Supports CPU_Cut mode for reducing current consumption when the CPU is inactive.
<< Other >>
Accepts a 12 MHz/24 MHz crystal resonator for clock input. (built-in Oscillator circuit and 1M
feedback resistor)
Dedicated pin for 12 MHz, 24 MHz, or 48 MHz clock input.
Triple-power supply system: 3.3 V, 1.8 V and variable CPU interface power
Package type: PFBGA5UX60 (S1R72V17B00A***)
PFBGA8UX81 (S1R72V17B00B***)
QFP14-80 (S1R72V17F00C***)
Guaranteed operation temperature range: –40°C to 85°C
* This LSI is not designed to resist radiation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S1R72V17B00A20 制造商:Epson Electronics America Inc 功能描述:USB HS HOST/DEVICE CONTROLLER,
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