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參數(shù)資料
| 型號： | S1R72V17B00A |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| 封裝： | 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60 |
| 文件頁數(shù)： | 27/45頁 |
| 文件大小： | 3044K |
| 代理商： | S1R72V17B00A |
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6. Functional Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
13
6.2 USB Device Control
The following describes the USB device functions.
6.2.1
Endpoints
The LSI stipulated herein has the endpoint for control transfer (EP0) and five general-purpose endpoints
(EPa, EPb, and EPe). The endpoints EPa, EPb, EPc, EPd, and EPe can each be used simultaneously as
endpoints for Bulk, Interrupt, and Isochronous transfers. The alarm endpoint function incorporated in the
LSI to generate an alarm when a transaction is issued from the USB host also permits the user system to
have up to 15 IN endpoints and up to 15 OUT endpoints, not including the endpoint EP0. The alarm
endpoint function notifies the firmware of a state by returning a NAK response for the transaction issued to
any endpoint other than the active endpoints set in EPa, EPb, EPc, EPd, and/or EPe.
The hardware of the LSI provides endpoints for the purpose of transaction management. However, it
does not provide management functions for the interfaces defined in the USB standard (hereinafter
referred to as the “USB-defined interface”). The USB-defined interface should be implemented by the
user firmware. Set up and combine endpoints as appropriate for the descriptor definitions specific to
the device, to configure the USB-defined interface.
Each endpoint has fixed basic setup items determined by the USB-defined interface and the variable
control items and status to be controlled for each transfer. The basic setup items should be set up when
initializing the chip or switching USB-defined interfaces from one to another.
Table 6.4 lists the basic setup items for the endpoint EP0 (default control pipe).
The endpoint EP0 shares the register set and FIFO area for transfers in IN and OUT directions. The
direction of data transaction should be set by the firmware as appropriate for the execution of the data
and status stages at the endpoint EP0.
Any desired transaction can be performed by joining to the FIFO area described later. First, set
AREA0StartAdrs_H,L and AREA0EndAdrs_H,L to reserve memory space for the FIFO area to be used.
After initializing the FIFO area with AREA0FIFO_Clr, set up AREA0Join_1.JoinEP0CH0 for the FIFO
area zero. No data transfers via a FIFO area can be performed until this joining process is executed.
Table 6.4 Basic Setup Items of the Endpoint EP0
Item
Register/Bit
Description
Max. packet size
D_EP0MaxSize
Sets the max packet size.
Set MaxSize to 8, 16, 32, or 64 for operation in
FS mode, or 64 for operation in HS mode.
FIFO area
AREA0StartAdrs_H,
AREA0StartAdrs _L,
AREA0EndAdrs _H,
AREA0EndAdrs _L
Sets an area to be allocated for the endpoint EP0
with the specified FIFO addresses.
Make sure the FIFO area is allocated memory
space greater than the max packet size.
For detailed information on how to allocate a
FIFO area, refer to the section in which FIFOs
are discussed.
FIFO area join
AREA0Join_1.JoinEP0CH0
Joins the endpoint EP0 to the allocated area.
Make sure endpoint EP0 is joined to AREA0.
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