參數(shù)資料
型號(hào)： S1R72V17B00A
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA60
封裝： 5 X 5 MM, 0.50 MM PITCH, PLASTIC, TFBGA-60
文件頁(yè)數(shù)： 22/45頁(yè)
文件大?。?/td> 3044K
代理商： S1R72V17B00A
5. Pin Description
S1R72V17*** Technical Manual (Rev.1.6)
EPSON
9
50
E9
E8
CD14
BI
Hi-Z
2mA
51
D8
C6
CD15
BI
Hi-Z
2mA
The internal register can be set to operate the XINT pin in 1/0 mode or in Hi-Z/0 mode.
To use an external clock by feeding it from the CLKIN pin, attach the XI pin to the GND potential and leave the XO pin
open. To use the internal oscillator of the LSI, connect a crystal resonator and oscillator circuit to the XI and XO pins and
attach the CLKIN pin to the GND potential.
PD: Pull Down
PU: Pull Up
POWER
QFP14
PFBGA8
PFBGA5
Name
Voltage
RESET
5,70,74
A3,A6,C2
A5,B3,C2
HVDD
3.3V
Power supply for the USB, and I/O
1,19,33,42,59,
65,76
A2,A8,C3,C8,
H1,H9
A2,A7,C7,G2
LVDD
1.8V
Power supply for the internal circuit,
Power supply for TEST I/O, power
supply for OSC
13,31,46,53
C6,F1,H6
D7
CVDD
3.3 to 1.8V
Power supply for CPU interface I/O
2,12,20,32,41,
45,55,56,66,
68,72,77
B1,B2,B4,B5,
B6,B7,B8,E2,
E7,J2,J8
B2,B4,B5,B6,
B7,G7
VSS
0V
GND
52,61,62,63,
64,69,78,79,
80
A1,A9,D4,D5,
D6,E4,E5,E6,
F4,F5,F6,J1,J9
A1
N.C.
0V
N.C. (Connect this pin to GND)
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