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參數(shù)資料
| 型號： | RM7065 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| 中文描述： | RM7065A⑩微處理器與片上二級高速緩存的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大小： | 776K |
| 代理商： | RM7065 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
42
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
7
Recommended Operating Conditions
Notes
1.
2.
3.
VccIO should not exceed VccInt by greater than 2.0 V during the power-up sequence.
Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG
test mode. Refer to the RM7065A Family Users Manual, Appendix E.
VccP must be connected to VccInt through a passive filter circuit. See RM7000 Family User
’
s Manual for
recommended circuit.
4.
CPU Speed
300 - 350 MHz
Temperature
0
°
C to +85
°
C
(Case)
Vss
0V
VccInt
1.65V
±
50 mV
VccIO
3.3 V
±
150 mV
or
2.5 V
±
200 mV
VccP
1.65V
±
50 mV
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