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參數(shù)資料
| 型號： | RM7065 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| 中文描述： | RM7065A⑩微處理器與片上二級高速緩存的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 25/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
25
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
The RM7065A cache attributes for the instruction, data, internal secondary caches are summarized
in Table 6.
Table 6 Cache Attributes
Attribute
Size
Associativity
Replacement
Algorithm
Line size
Index
4.21 Cache Locking
The RM7065A allows critical code or data fragments to be locked into the primary and secondary
caches. The user has complete control over the locking function. For instruction and data
fragments in the primary caches, locking is accomplished by setting either or both of the cache
lock enable bits and specifying the set in the CP0 ECC register, then executing either a load
instruction for data, or a Fill_I cache operation for instructions.
Only sets A and B within each cache can be locked. Locking within the secondary works
identically to the primaries using a separate secondary lock enable bit and the same set selection
field. As with the primaries, only sets A and B can be locked. Table 7 summarizes the cache
locking capabilities.
Instruction
16KB
4-way
cyclic
Data
16KB
4-way
cyclic
Secondary
256KB
4-way
cyclic
32 byte
vAddr
11..0
pAddr
35..12
n.a.
32 byte
vAddr
11..0
pAddr
35..12
write-back,
write-through
non-blocking (2
outstanding)
32 byte
pAddr
15..0
pAddr
35..16
block write-
back, bypass
non-blocking
(data only, 2
outstanding)
Tag
Write policy
read policy
n.a.
read order
critical word first
critical word first critical word
first
sequential
n.a.
write order
miss restart
following:
Parity
NA
complete line
sequential
first double (if
waiting for data)
per word
per byte
per
doubleword
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