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參數(shù)資料
| 型號： | RM7065 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| 中文描述： | RM7065A⑩微處理器與片上二級高速緩存的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 12/52頁 |
| 文件大?。?/td> | 776K |
| 代理商： | RM7065 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
12
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
4
Hardware Overview
The RM7065A offers a high-level of integration targeted at high-performance embedded
applications. The key elements of the RM7065A are described throughout this section.
CPU Registers
4.1
The RM7065A CPU contains 32 general purpose registers (GPR), two special purpose registers
for integer multiplication and division, and a program counter; there are no condition code bits.
Figure 2 shows the user visible state.
Figure 2 CP0 Registers
General Purpose Registers
63
4.2
Superscalar Dispatch
The RM7065A incorporates a superscalar dispatch unit that allows it to issue up to two
instructions per cycle. For purposes of instruction issue, the RM7065A defines four classes of
instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the
function
, or F, pipeline and the
memory
, or M, pipeline. Note however that the M pipe can execute
integer as well as memory type instructions.
Table 1 Instruction Issue Rules
F Pipe
one of:
integer, branch, floating-point,
integer mul, div
0
Multiply/Divide Registers
63
0
r1
r2
0
HI
63
0
LO
Program Counter
63
0
r29
r30
r31
PC
M Pipe
one of:
integer, load/store
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