參數(shù)資料
型號(hào)： RM5261A
廠商： PMC-Sierra, Inc.
英文描述： RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary
中文描述： RM5261A⑩微處理器與64位系統(tǒng)總線的數(shù)據(jù)資料的初步
文件頁(yè)數(shù)： 23/42頁(yè)
文件大?。?/td> 683K
代理商： RM5261A
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
23
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
ExtRqst*
and
Release*
are used to transfer control of the
SysAD
and
SysCmd
buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*
. The RM5261A responds by asserting
Release*
to release the system interface to slave
state.
ValidOut*
and
ValidIn*
are used by the RM5261A and the external device respectively to
indicate that there is a valid address, a command, or data on the
SysAD
and
SysCmd
buses. The
RM5261A asserts
ValidOut*
when it is driving these buses with a valid address, a command, or
data, and the external device drives
ValidIn*
when it has control of the buses and is driving a valid
address, a command, or data.
3.25 Non-overlapping System Interface
The RM5261A implements a non-overlapping system interface, meaning that only one processor
request may be outstanding at a time and that the request must be serviced by an external device
before the RM5261A issues another request. The RM5261A can issue read and write requests to
an external device, whereas an external device can issue null and write requests to the RM5261A.
For processor reads the RM5261A asserts
ValidOut*
and simultaneously drives the address and
read command on the
SysAD
and
SysCmd
buses respectively. If the system interface has
RdRdy*
asserted, then the processor tristates its drivers and releases the system interface to the slave state
by asserting
Release*
. The external device can then begin sending data to the RM5261A.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is 4 cycles (
ValidOut*
to
ValidIn*
), and the response data pattern is DDDD, indicating
that data can be transferred on every clock with no wait states in-betwee
n.
Figure 7 Processor Block Read
Figure 8 shows a processor block write using write response pattern DDDD, or code 0, of the boot-
time mode select options.
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Addr
Data0
Data1
Data2
Data3
Read
NData
NData
NData
NEOD
相關(guān)PDF資料
PDF描述
RM5261A-250-H RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary
RM5261A-300-H CONNECTOR ACCESSORY
RM5261A-300-HI CONNECTOR ACCESSORY
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RM5261 RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
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