- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378162 > RM5261A (PMC-Sierra, Inc.) RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary PDF資料下載
參數(shù)資料
| 型號： | RM5261A |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
| 中文描述： | RM5261A⑩微處理器與64位系統(tǒng)總線的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 22/42頁 |
| 文件大小： | 683K |
| 代理商： | RM5261A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
22
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
Figure 6
Typical Embedded System Block Diagram
3.22 System Address/Data Bus
The 64-bit System Address Data (
SysAD
) bus is used to transfer addresses and data between the
RM5261A and the rest of the system. It is protected with an 8-bit parity check bus (
SysADC)
. The
system interface is configurable to allow easy interfacing to memory and I/O systems of varying
frequencies.
The Block Write data rate, Non-block Write protocol, and the Output Drive strength are
programmable at Boot time via the
Mode Control
bits. The rate at which the processor receives
data is also fully controlled by the external device.
3.23 System Command Bus
The RM5261A interface has a 9-bit System Command (
SysCmd
) bus. The command bus
indicates whether the
SysAD
bus carries address or data information on a per-clock basis. If the
SysAD
carries address, the
SysCmd
bus indicates what type of transaction is to take place (for
example, a read or write). If the
SysAD
carries data, the
SysCmd
bus provides information about
the data (for example, this is the last data word transmitted, or the data contains an error). The
SysCmd
bus is bidirectional to support both processor requests and external requests to the
RM5261A. Processor requests are initiated by the RM5261A and responded to by an external
device. External requests are issued by an external device and require the RM5261A to respond.
The RM5261A supports one- to eight-byte transfers as well as block transfers on the
SysAD
bus.
In the case of a sub-double word transfer, the three low-order address bits give the byte address of
the transfer, and the
SysCmd
bus indicates the number of bytes being transferred.
3.24 Handshake Signals
There are six handshake signals on the system interface. Two of these,
RdRdy*
and
WrRdy*
, are
used by an external device to indicate to the RM5261A whether it can accept a new read or write
transaction. The RM5261A samples these signals before deasserting the address on read and write
requests.
RM5261A
Memory I/O
Controller
Flash/
Boot
Rom
x
x
72
PCI Bus
72
8
23
Latch
DRAM
Control
Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5261A-250-H | RM5261A⑩ Microprocessor with 64-Bit System Bus Data Sheet Preliminary |
| RM5261A-300-H | CONNECTOR ACCESSORY |
| RM5261A-300-HI | CONNECTOR ACCESSORY |
| RM5261A-350-H | CONNECTOR ACCESSORY |
| RM5261 | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5271-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。