參數(shù)資料
型號： RM5261
廠商： PMC-Sierra, Inc.
英文描述： RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
中文描述： RM5261⑩微處理器與64位系統(tǒng)總線的數(shù)據(jù)資料發(fā)布
文件頁數(shù)： 20/40頁
文件大?。?/td> 683K
代理商： RM5261
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
20
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
3. Write-through with write allocate
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the
write-back
bit of the cache line unchanged. If the cache lookup
misses, the target line is first brought into the cache and then the write is performed as above.
4. Write-through without write allocate
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated and main
memory is written, leaving the
write-back
bit of the cache line unchanged. If the cache lookup
misses, then only main memory is written.
The most commonly used write policy is write-back, where a store to a cache line does not
immediately cause the main memory to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software can, however, select write-through on a
per-page basis when appropriate, such as for frame buffers.
Associated with the data cache is the store buffer. When the RM5261 executes a store instruction,
this single-entry buffer gets written with the store data while the tag comparison is performed. If
the tag matches, then the data is written into the data cache in the next cycle that the data cache is
not accessed (the next non-load cycle). The store buffer allows the RM5261 to execute a store
every processor cycle and to perform back-to-back stores without penalty. In the event of a store
immediately followed by a load to the same address, a combined merge and cache write occurs
such that no penalty is incurred. The RM5261 cache attributes for both the instruction and data
caches are summarized in Table 3.
Table 3 Cache Attributes
Characteristics
Size
Organization
Line size
Index
Instruction
32KB
2-way set associative
32B
vAddr
11..0
pAddr
31..12
n.a.
sub-block
sequential
entire line
per-word
set A
Data
32KB
2-way set associative
32B
vAddr
11..0
pAddr
31..12
write-back/write-through
sub-block
sequential
first double
per-byte
set A
Tag
Write policy
Read order
Write order
miss restart after transfer of
Parity
Cache locking
相關(guān)PDF資料
PDF描述
RM5261-200-Q RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-200-QI RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-250-Q RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261-266-Q RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
RM7065 RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RM5261-200Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5261-225Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5261-250Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5261-250Q-C001 制造商:PMC Sierra from Components Direct 功能描述:RM5261-250Q-C001, MICROPROCESSOR 64-BIT 0.25 UM CMOS TECHNOL - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261-250Q-C001, Microprocessor 64-Bit 0.25 um CMOS Technology 3.3V 208-Pin PQFP
RM5261-266Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
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