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參數(shù)資料
| 型號： | RM5261 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | RM5261⑩微處理器與64位系統(tǒng)總線的數(shù)據(jù)資料發(fā)布 |
| 文件頁數(shù)： | 12/40頁 |
| 文件大小： | 683K |
| 代理商： | RM5261 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
12
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-
operand integer multiply/divide operations, and the program counter (PC).
Pipeline
3.4
For integer operations, loads, stores, and other non-floating-point operations, the RM5261
implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261 implements
an extended 7-stage pipeline for floating-point operations.
The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the
pipeline clock.
Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure, up to five integer
instructions can be executing simultaneously.
Figure 3 Pipeline
3.5
Register File
The RM5261 has thirty-two general purpose registers with register location 0 (r0) hard-wired to a
zero value. These registers are used for scalar integer operations and address calculation. The
register file has two read ports and one write port and is fully bypassed to minimize operation
latency in the pipeline.
ALU
3.6
The RM5261 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder
performs address calculations in addition to arithmetic operations. The logic unit performs all
logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in a single processor cycle.
I0
I1
I2
I3
I4
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
2I
1I
1R
2R
1A
2A
1D
2D
1W
2W
one cycle
1I-1R:
2I:
2R:
1A:
1A:
2A-2A:
1A-2A:
1D:
2W:
Instruction cache access
Instruction virtual to physical address translation
Register file read, Bypass calculation, Instruction decode, Branch address calculation
Issue or slip decision, Branch decision
Data virtual address calculation
Integer add, logical, shift
Store Align
Data cache access and load align
Data virtual to physical address translation
Register file write
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-225Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5261-250Q-C001 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261-250Q-C001, MICROPROCESSOR 64-BIT 0.25 UM CMOS TECHNOL - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261-250Q-C001, Microprocessor 64-Bit 0.25 um CMOS Technology 3.3V 208-Pin PQFP |
| RM5261-266Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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