- 您現在的位置：買賣IC網 > PDF目錄378162 > RM5261-266-Q (PMC-SIERRA INC) RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released PDF資料下載
參數資料
| 型號： | RM5261-266-Q |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 266 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | POWER, QFP-208 |
| 文件頁數： | 34/40頁 |
| 文件大?。?/td> | 683K |
| 代理商： | RM5261-266-Q |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
34
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
9.3
System Interface Parameters
1
9.4
Boot-Time Interface Parameters
Parameter
Symbol
t
DO
Conditions
200
–
266 MHz
Units
ns
Min
1.0
Max
4.5
Data Output
2,3
mode14:13 = 10
5
(fastest)
mode14:13 = 11
5
1.0
5.0
ns
mode14:13 = 00
5
1.0
5.5
ns
mode14:13 = 01
5
(slowest)
t
rise
= see above table
t
fall
= see above table
1.0
6.0
ns
Data Setup
4
t
DS
2.5
ns
Data Hold
4
Notes
1.
Timings are measured from 1.5 V of the clock to 1.5 V of the signal.
2.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for a
theoretical no load condition - untested.
3.
Data Output timing applies to all signal pins whether tristate I/O or output only.
4.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5.
Only mode 14:13 = 00 is tested and guaranteed.
t
DH
1.0
ns
Parameter
Mode Data Setup
Symbol
t
DS
(M)
t
DH
(M)
Min
4
Max
Units
SysClock cycles
Mode Data Hold
0
SysClock cycles
相關PDF資料 |
PDF描述 |
|---|---|
| RM7065 | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| RM7065A | 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7065A-300T | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| RM7065A-350T | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| RM805 | LEAD FREE 8-BIT 50V SER-IN LATCHED DRV |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RM5261A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復。