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參數(shù)資料
| 型號(hào)： | RM5261-266-Q |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 266 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | POWER, QFP-208 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 683K |
| 代理商： | RM5261-266-Q |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
19
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
3.18 Instruction Cache
The RM5261 incorporates a two-way set associative on-chip instruction cache. This virtually
indexed, physically tagged cache is 32 KB in size and is protected with word parity.
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and a single parity bit.
The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits
per cycle allows the instruction cache to supply two instructions per cycle to the superscalar
dispatch unit. For typical code sequences where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop, the entire bandwidth available from
the instruction cache will be consumed.
Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight
instructions (32 bytes) to maximize the performance of communication between the processor and
the memory system.
Like the R4650, the RM5261 supports cache locking. The contents of one set of the cache, set A,
can be
locked
by setting a bit in the coprocessor 0 Status register. Locking the set prevents its
contents from being overwritten by a subsequent cache miss. Refill will occur only into set B. This
mechanism allows the programmer to lock critical code into the cache thereby guaranteeing
deterministic behavior for the locked code sequence.
3.19 Data Cache
For fast, single cycle data access, the RM5261 includes a 32 KB on-chip data cache that is two-
way set associative with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is
virtually indexed and physically tagged to allow simultaneous address translation and data cache
access.
Cache protocols supported for the data cache are:
1. Uncached
Data loads and instruction fetches from uncached memory space are brought in from the main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data stores to uncached memory space go directly to the main memory without updating the
data cache.
2. Write-back
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
the target address is cache resident. If it is resident, the cache contents are updated, and the
cache line is marked for later write-back. If the cache lookup misses, the target cache line is
first brought into the cache and then the write is performed as above.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5261A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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