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參數(shù)資料
| 型號： | RM5261-266-Q |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 266 MHz, MICROPROCESSOR, PQFP208 |
| 封裝： | POWER, QFP-208 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 683K |
| 代理商： | RM5261-266-Q |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
22
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
carries address, the
SysCmd
bus indicates what type of transaction is to take place (for example, a
read or write). If the
SysAD
carries data, the
SysCmd
bus provides information about the data (for
example, this is the last data word transmitted, or the data contains an error). The
SysCmd
bus is
bidirectional to support both processor requests and external requests to the RM5261. Processor
requests are initiated by the RM5261 and responded to by an external device. External requests are
issued by an external device and require the RM5261 to respond.
The RM5261 supports one- to eight-byte transfers as well as block transfers on the
SysAD
bus. In
the case of a sub-double word transfer, the three low-order address bits give the byte address of the
transfer, and the
SysCmd
bus indicates the number of bytes being transferred.
3.24 Handshake Signals
There are six handshake signals on the system interface. Two of these,
RdRdy*
and
WrRdy*
, are
used by an external device to indicate to the RM5261 whether it can accept a new read or write
transaction. The RM5261 samples these signals before deasserting the address on read and write
requests.
ExtRqst*
and
Release*
are used to transfer control of the
SysAD
and
SysCmd
buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*
. The RM5261 responds by asserting
Release*
to release the system interface to slave
state.
ValidOut*
and
ValidIn*
are used by the RM5261 and the external device respectively to indicate
that there is a valid address, command or data on the
SysAD
and
SysCmd
buses. The RM5261
asserts
ValidOut*
when it is driving these buses with a valid address, a command or data, and the
external device drives
ValidIn*
when it has control of the system interface and is driving a valid
address, command or data.
3.25 Non-overlapping System Interface
The RM5261 requires a non-overlapping system interface, compatible with the R5000. This means
that only one processor request may be outstanding at a time and that the request must be serviced
by an external device before the RM5261 issues another request. The RM5261 can issue read and
write requests to an external device, whereas an external device can issue null and write requests to
the RM5261.
For processor reads the RM5261 asserts
ValidOut*
and simultaneously drives the address and
read command on the
SysAD
and
SysCmd
buses respectively. If the system interface has
RdRdy*
asserted, then the processor tristates its drivers and releases the system interface to the slave state
by asserting
Release*
. The external device can then begin sending data to the RM5261.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is four cycles (
ValidOut*
to
ValidIn*
), and the response data pattern is DDDD, indicating
that data can be transferred on every clock with no wait states in-between.
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|---|---|
| RM5261A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
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| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
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| RM5270-200S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
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