參數(shù)資料
型號(hào)： RM5261-266-Q
廠商： PMC-SIERRA INC
元件分類： 微控制器/微處理器
英文描述： RM5261⑩ Microprocessor with 64-Bit System Bus Data Sheet Released
中文描述： 64-BIT, 266 MHz, MICROPROCESSOR, PQFP208
封裝： POWER, QFP-208
文件頁(yè)數(shù)： 15/40頁(yè)
文件大小： 683K
代理商： RM5261-266-Q
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002241, Issue 1
15
RM5261
Microprocessor with 64-Bit System Bus Data Sheet
Released
3.10 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions (
LDC1
and
SDC1
) the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store
doubleword instruction in every cycle.
The floating-point control register space contains two registers; one for determining configuration
and revision information for the coprocessor and one for control and status information. These are
primarily used for diagnostic software, exception handling, state saving and restoring, and control
of rounding modes. To support superscalar operation, the FGR has four read ports and two write
ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports
and one write port are used to support the combined multiply-add instruction while the fourth read
and second write port allows a concurrent floating-point load or store.
3.11 System Control Co-processor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is
responsible for the virtual memory sub-system, the exception control system, and the diagnostics
capability of the processor. In the MIPS architecture, the system control co-processor (and thus the
kernel software) is implementation dependent.
The memory management unit controls the virtual memory system page mapping. It consists of an
instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint
instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual
memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5261 incorporates all system control co-processor (CP0) registers on-chip. These registers
provide the path through which the virtual memory system
’
s page mapping is examined and
modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261 includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
fcvt.l.d
fcmp
fmov
fmovc
fabs
fneg
Note:
4
1
1
1
1
1
1
1
1
1
1
1
Numbers are represented as single/double precision format.
Operation
Latency
Repeat Rate
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