參數(shù)資料
型號(hào)： RM5231
廠商： PMC-Sierra, Inc.
英文描述： RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
中文描述： RM5231⑩微處理器與32位系統(tǒng)總線的數(shù)據(jù)資料發(fā)布
文件頁(yè)數(shù)： 9/39頁(yè)
文件大?。?/td> 630K
代理商： RM5231
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002165, Issue 1
9
RM5231
Microprocessor with 32-bit System Bus Data Sheet
Released
1
Features
Dual Issue superscalar microprocessor
150, 200, & 250 MHz operating frequencies
300 Dhrystone2.1 MIPS
System interface optimized for embedded applications
32-bit system interface lowers total system cost
High-performance write protocols maximize uncached write bandwidth
Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
2.5 V core with 3.3 V IOs
IEEE 1149.1 JTAG boundary scan
Integrated on-chip caches
32 KB instruction and 32 KB data
—
2 way set associative
Per set locking
Virtually indexed, physically tagged
Write-back and write-through on a per page basis
Pipeline restart on first doubleword for data cache misses
Integrated memory management unit
Fully associative joint TLB (shared by I and D translations)
48 dual entries map 96 pages
Variable page size (4 KB to 16 MB in 4x increments)
High-performance floating-point unit
—
up to 500 MFLOPS
Single cycle repeat rate for common single-precision operations and some double pre-
cision operations
Two cycle repeat rate for double-precision multiply and double precision combined
multiply-add operations
Single cycle repeat rate for single-precision combined multiply-add operation
MIPS IV instruction set
Floating point multiply-add instruction increases performance in signal processing
and graphics applications
Conditional moves to reduce branch frequency
Index address modes (register + register)
Embedded application enhancements
Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply
instruction
I and D cache locking by set
Optional dedicated exception vector for interrupts
Fully static 0.25 micron CMOS design with power down logic
Standby reduced power mode with
WAIT
instruction
2.5 V core with 3.3 V I/O
128-pin Power-Quad 4 (QFP) package
相關(guān)PDF資料
PDF描述
RM5231-200-Q RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
RM5231-250-Q RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
RM5231A RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
RM5231A-250-H RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
RM5231A-300-H RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RM5231-150Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-150Q-C001 制造商:PMC-Sierra 功能描述:
RM5231-200Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-225Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-250Q 制造商:QED 功能描述:Microprocessor, 64 Bit, 128 Pin, Plastic, QFP
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