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參數(shù)資料
| 型號(hào)： | RM5231 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| 中文描述： | RM5231⑩微處理器與32位系統(tǒng)總線的數(shù)據(jù)資料發(fā)布 |
| 文件頁(yè)數(shù)： | 25/39頁(yè) |
| 文件大小： | 630K |
| 代理商： | RM5231 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002165, Issue 1
25
RM5231
Microprocessor with 32-bit System Bus Data Sheet
Released
low frequency operation allows the initialization information to be kept in a low cost EPROM or a
system interface ASIC.
Immediately after the
VccOK
signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock run continuously from the
assertion of
VccOK
.
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when
VccOK
is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream
Mode
bit
0
Description
Reserved: Must be zero
Mode
bit
14:13
Description
Output driver strength - 100% = fastest
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
Reserved: Must be zero
4:1
Write-back data rate (W = write data transfer, x = wait
state)
0: WWWWWWWW
1: WWxWWxWWxWWx
2: WWxxWWxxWWxxWWxx
3: WxWxWxWxWxWxWxWx
4: WWxxxWWxxxWWxxxWWxxx
5: WWxxxxWWxxxxWWxxxxWWxxxx
6: WxxWxxWxxWxxWxxWxxWxxWxx
7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx
8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx
9-15 reserved
Pclock to SysClock Multiplier
Mode Bits 7:5 Mode Bit 20=0 Mode Bit 20=1
000 Multiply by 2 n/a
001 Multiply by 3 n/a
010 Multiply by 4 n/a
011 Multiply by 5 Multiply by 2.5
100 Multiply by 6 n/a
101 Multiply by 7 Multiply by 3.5
110 Multiply by 8 n/a
111 Multiply by 9 Multiply by 4.5
Specifies byte ordering. Logically ORed with
BigEndian input signal.
0: Little endian
1: Big endian
Non-Block Write Protocol
00: R4000 compatible
01: reserved
10: pipelined
11: write re-issue
Timer Interrupt Enable/Disable
0: Enable the timer interrupt on
Int5*
1: Disable the timer interrupt on
Int5*
Reserved: Must be zero
15
7:5
17:16
System configuration identifiers - software
visible in Config[21..20] register
8
19:18
Reserved: Must be zero
10:9
20
Select SysClock to PClock Multiply Mode
0: Integer Multipliers
1: Half-Integer Multipliers
11
21
Reserved: Must be one
12
255:22
Reserved: Must be zero
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5231-200-Q | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| RM5231-250-Q | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| RM5231A | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-250-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-300-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5231-150Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5231-150Q-C001 | 制造商:PMC-Sierra 功能描述: |
| RM5231-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5231-225Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5231-250Q | 制造商:QED 功能描述:Microprocessor, 64 Bit, 128 Pin, Plastic, QFP |
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