參數(shù)資料
型號(hào)： RM5231
廠商： PMC-Sierra, Inc.
英文描述： RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
中文描述： RM5231⑩微處理器與32位系統(tǒng)總線的數(shù)據(jù)資料發(fā)布
文件頁數(shù)： 13/39頁
文件大小： 630K
代理商： RM5231
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002165, Issue 1
13
RM5231
Microprocessor with 32-bit System Bus Data Sheet
Released
Table 1 Integer Multiply/Divide Operations
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (
MFHI
/
MFLO
) instructions.
In addition to the baseline MIPS IV integer multiply instructions, the RM5231 also implements the
3 operand multiply instruction,
MUL
. This instruction specifies that the multiply result go directly
to the integer register file rather than the Lo register. The portion of the multiply that would have
normally gone into the Hi register is discarded. For applications where it is known that the upper
half of the multiply result is not required, using the
MUL
instruction eliminates the necessity of
executing an explicit
MFLO
instruction.
Also included in the RM5231 are the multiply-add instructions,
MADU
/
MAD
. This instruction
multiplies two operands and adds the resulting product to the current contents of the Hi and Lo
registers. The multiply-accumulate operation is the core primitive of almost all signal processing
algorithms allowing the RM5231 to eliminate the need for a separate DSP engine in many
embedded applications.
Floating-Point Co-Processor
3.8
The RM5231 incorporates a high-performance fully pipelined floating-point co-processor which
includes a floating-point register file and autonomous execution units for multiply/add/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the integer unit. The superscalar capabilities of the RM5231 allow floating-point
computation instructions to issue concurrently with integer instructions.
Floating-Point Unit
3.9
The RM5231 floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add
operations is supported.
The RM5231 maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Opcode
MULT/U,
MAD/U
Operand
Size
16 bit
32 bit
16 bit
32 bit
any
Latency
3
4
3
4
7
Repeat
Rate
2
3
2
3
6
Stall
Cycles
0
0
1
2
0
MUL
DMULT,
DMULTU
DIV, DIVD
DDIV,
DDIVU
any
any
36
68
36
68
0
0
相關(guān)PDF資料
PDF描述
RM5231-200-Q RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
RM5231-250-Q RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released
RM5231A RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
RM5231A-250-H RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
RM5231A-300-H RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RM5231-150Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-150Q-C001 制造商:PMC-Sierra 功能描述:
RM5231-200Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-225Q 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor
RM5231-250Q 制造商:QED 功能描述:Microprocessor, 64 Bit, 128 Pin, Plastic, QFP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*