參數(shù)資料
型號： RLP03N06CLE
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： JFETs
英文描述： 0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs
中文描述： 60 V, 6 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB
文件頁數(shù)： 12/13頁
文件大小： 188K
代理商： RLP03N06CLE
12
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
LEAD NO. 1
-
GATE
LEAD NO. 3
-
SOURCE
TERM. 4
-
DRAIN
b
2
E
D
L
3
L
e
b
1
b
1
3
A
L
c
SEATING
PLANE
BACK VIEW
2
H
1
A
1
b
3
e
1
J
1
L
1
TERM. 4
0.265
(6.7)
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
0.265 (6.7)
0.070 (1.8)
0.118 (3.0)
0.063 (1.6)
0.090 (2.3)
0.063 (1.6)
0.090 (2.3)
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.086
0.094
2.19
2.38
-
A
1
b
0.018
0.022
0.46
0.55
4, 5
0.028
0.032
0.72
0.81
4, 5
b
1
b
2
b
3
c
0.033
0.040
0.84
1.01
4
0.205
0.215
5.21
5.46
4, 5
0.190
-
4.83
-
2
0.018
0.022
0.46
0.55
4, 5
D
0.270
0.290
6.86
7.36
-
E
0.250
0.265
6.35
6.73
-
e
0.090 TYP
2.28 TYP
7
e
1
H
1
J
1
L
0.180 BSC
4.57 BSC
7
0.035
0.045
0.89
1.14
-
0.040
0.045
1.02
1.14
-
0.100
0.115
2.54
2.92
-
L
1
L
2
L
3
0.020
-
0.51
-
4, 6
0.025
0.040
0.64
1.01
3
0.170
-
4.32
-
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L
3
and b
3
dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L
1
is the terminal length for soldering.
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 5 dated 10-95.
相關(guān)PDF資料
PDF描述
RLD03N06CLE 0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs
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