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Page xvi of liv
12.3.23
Timer Cycle Data Register (TCDR) ................................................................. 542
12.3.24
Timer Cycle Buffer Register (TCBR)............................................................... 543
12.3.25
Timer Interrupt Skipping Set Register (TITCR)............................................... 543
12.3.26
Timer Interrupt Skipping Counter (TITCNT)................................................... 545
12.3.27
Timer Buffer Transfer Set Register (TBTER) .................................................. 546
12.3.28
Timer Dead Time Enable Register (TDER) ..................................................... 548
12.3.29
Timer Waveform Control Register (TWCR) .................................................... 549
12.3.30
Bus Master Interface......................................................................................... 550
12.4
Operation .......................................................................................................................... 551
12.4.1
Basic Functions................................................................................................. 551
12.4.2
Synchronous Operation..................................................................................... 557
12.4.3
Buffer Operation ............................................................................................... 559
12.4.4
Cascaded Operation .......................................................................................... 563
12.4.5
PWM Modes..................................................................................................... 568
12.4.6
Phase Counting Mode....................................................................................... 573
12.4.7
Reset-Synchronized PWM Mode ..................................................................... 580
12.4.8
Complementary PWM Mode............................................................................ 583
12.4.9
A/D Converter Start Request Delaying Function.............................................. 623
12.4.10
TCNT Capture at Crest and/or Trough in
Complementary PWM Operation ..................................................................... 627
12.5
Interrupt Sources...............................................................................................................628
12.5.1
Interrupt Sources and Priorities ........................................................................ 628
12.5.2
Activation of Direct Memory Access Controller .............................................. 630
12.5.3
A/D Converter Activation................................................................................. 630
12.6
Operation Timing.............................................................................................................. 632
12.6.1
Input/Output Timing ......................................................................................... 632
12.6.2
Interrupt Signal Timing .................................................................................... 639
12.7
Usage Notes ...................................................................................................................... 643
12.7.1
Module Standby Mode Setting ......................................................................... 643
12.7.2
Input Clock Restrictions ................................................................................... 643
12.7.3
Caution on Period Setting ................................................................................. 644
12.7.4
Contention between TCNT Write and Clear Operations.................................. 644
12.7.5
Contention between TCNT Write and Increment Operations........................... 645
12.7.6
Contention between TGR Write and Compare Match ...................................... 646
12.7.7
Contention between Buffer Register Write and Compare Match ..................... 647
12.7.8
Contention between Buffer Register Write and TCNT Clear ........................... 648
12.7.9
Contention between TGR Read and Input Capture........................................... 649
12.7.10
Contention between TGR Write and Input Capture.......................................... 650
12.7.11
Contention between Buffer Register Write and Input Capture ......................... 651