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Page xxii of liv
19.4.4
Data Read Control Register (DRCR)................................................................ 968
19.4.5
Data Read Command Setting Register (DRCMR)............................................ 970
19.4.6
Data Read Extended Address Setting Register (DREAR) ................................ 971
19.4.7
Data Read Option Setting Register (DROPR) .................................................. 973
19.4.8
Data Read Enable Setting Register (DRENR) .................................................. 974
19.4.9
SPI Mode Control Register (SMCR) ................................................................ 978
19.4.10
SPI Mode Command Setting Register (SMCMR) ............................................ 980
19.4.11
SPI Mode Address Setting Register (SMADR) ................................................ 981
19.4.12
SPI Mode Option Setting Register (SMOPR)................................................... 982
19.4.13
SPI Mode Enable Setting Register (SMENR) .................................................. 983
19.4.14
SPI Mode Read Data Register 0 (SMRDR0).................................................... 987
19.4.15
SPI Mode Read Data Register 1 (SMRDR1).................................................... 988
19.4.16
SPI Mode Write Data Register 0 (SMWDR0).................................................. 989
19.4.17
SPI Mode Write Data Register 1 (SMWDR1).................................................. 990
19.4.18
Common Status Register (CMNSR) ................................................................. 991
19.5
Operation .......................................................................................................................... 992
19.5.1
System Configuration ....................................................................................... 992
19.5.2
Address Map..................................................................................................... 993
19.5.3
32-bit Serial Flash Addresses............................................................................ 994
19.5.4
Data Alignment................................................................................................. 995
19.5.5
Operating Modes .............................................................................................. 996
19.5.6
External Address Space Read Mode................................................................. 996
19.5.7
Read Cache ..................................................................................................... 1001
19.5.8
SPI Operating Mode ....................................................................................... 1002
19.5.9
Transfer Format .............................................................................................. 1007
19.5.10
Data Format .................................................................................................... 1009
19.5.11
Data Pin Control ............................................................................................. 1017
19.5.12
SPBSSL Pin Control....................................................................................... 1019
19.5.13
Flags................................................................................................................ 1020
Section 20 I
2C Bus Interface 3.........................................................................1021
20.1
Features........................................................................................................................... 1021
20.2
Input/Output Pins............................................................................................................ 1023
20.3
Register Descriptions...................................................................................................... 1024
20.3.1
I
2C Bus Control Register 1 (ICCR1)............................................................... 1025
20.3.2
I
2C Bus Control Register 2 (ICCR2)............................................................... 1028
20.3.3
I
2C Bus Mode Register (ICMR)...................................................................... 1030
20.3.4
I
2C Bus Interrupt Enable Register (ICIER)..................................................... 1032
20.3.5
I
2C Bus Status Register (ICSR)....................................................................... 1034
20.3.6
Slave Address Register (SAR)........................................................................ 1037