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參數(shù)資料
| 型號： | R5F64211JFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 48/50頁 |
| 文件大?。?/td> | 777K |
| 代理商： | R5F64211JFB |
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125
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
An external clock source can not be prescaled.
Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
1. The synchronization logic on the input pins (
T1/T0) is shown in Figure 17-1 on page 124.
17.4
Register description
17.4.1
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is writ-
ten to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This
ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the
risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits
are cleared by hardware, and the Timer/Counters start counting simultaneously.
Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the
same prescaler and a reset of this prescaler will affect both timers.
PSR10
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM
–
PSR2
PSR10
GTCCR
Read/Write
R/W
RR
R
R/W
Initial Value
0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| R5F64211KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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| R5F64212JFB | 制造商:Renesas Electronics Corporation 功能描述: |
| R5F64212KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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