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參數(shù)資料
| 型號： | R5F64211JFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 43/50頁 |
| 文件大小： | 777K |
| 代理商： | R5F64211JFB |
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121
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between
TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare
units.
16.11.5
OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.6
OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultane-
ously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit registers” on
16.11.7
ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit registers” on
Bit
765
432
10
(0x89)
OCR1A[15:8]
OCR1AH
(0x88)
OCR1A[7:0]
OCR1AL
Read/Write
R/W
Initial Value
000
00
Bit
765
432
10
(0x8B)
OCR1B[15:8]
OCR1BH
(0x8A)
OCR1B[7:0]
OCR1BL
Read/Write
R/W
Initial Value
000
00
Bit
765
432
10
(0x87)
ICR1[15:8]
ICR1H
(0x86)
ICR1[7:0]
ICR1L
Read/Write
R/W
Initial Value
000
00
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PDF描述 |
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| R5F64211KFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
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| R5F6421GJFB | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F64211KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64211LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212JFB | 制造商:Renesas Electronics Corporation 功能描述: |
| R5F64212KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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