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參數(shù)資料
| 型號(hào)： | R5F64211JFB |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 777K |
| 代理商： | R5F64211JFB |
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98
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Figure 16-1. 16-bit Timer/Counter, block diagram
(1).
Note:
1. Refer to Figure 1-1 on page 2 and Figure 14-5 on page 66 for Timer/Counter1 pin placement and description.
16.2.1
Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are
described in the section ”Accessing 16-bit registers” on page 99. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in
the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked
with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
T1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time.
The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency out-
put on the Output Compare pin (OC1A/B). See ”O(jiān)utput Compare Units” on page 105.. The compare match event
will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt
request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”AC - Analog Comparator” on page
Clock Select
Timer/Counter
D
ATA
B
U
S
OCRnA
OCRnB
ICRn
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA
TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| R5F64211KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64211LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212JFB | 制造商:Renesas Electronics Corporation 功能描述: |
| R5F64212KFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F64212LFB | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
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