參數(shù)資料
型號(hào)： R5F64211JFB
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 36/50頁
文件大?。?/td> 777K
代理商： R5F64211JFB
114
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an inter-
rupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of
all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will
never occur between the TCNT1 and the OCR1x.
As Figure 16-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods.
Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be
equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively
changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x
pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be gen-
erated by setting the COM1x1:0 to three (See Table 16-4 on page 118). The actual OC1x value will only be visible
on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated
by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter
increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the
counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be cal-
culated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in
the phase and frequency correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously
low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output
will have the opposite logic values. If OCR1A is used to define the TOP value (WGM1[3:0] = 9) and COM1A1:0 = 1,
the OC1A output will toggle with a 50% duty cycle.
16.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T1) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Reg-
ister is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 16-10 shows a
timing diagram for the setting of OCF1x.
f
OCnxPFCPWM
fclk_I/O
2 NTOP
----------------------------
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R5F64211KFB 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F64211LFB 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F64212JFB 制造商:Renesas Electronics Corporation 功能描述:
R5F64212KFB 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
R5F64212LFB 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU
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