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參數(shù)資料
| 型號： | R5F213J5TNNP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, QCC40 |
| 封裝： | 5 X 5 MM, 0.40 MM PITCH, QFN-40 |
| 文件頁數(shù)： | 45/45頁 |
| 文件大?。?/td> | 440K |
| 代理商： | R5F213J5TNNP |
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9
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
In different addressing modes these address registers function as automatic increment and automatic decrement
(see document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for details).
4.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the
Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This
Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or inter-
rupts are enabled. The Stack Pointer must be set to point above 0x40. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return
address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the
Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clk
CPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F213J5TNNP#W4 | 功能描述:MCU 24KB ROM 2KB RAM 40-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/3x/3JT 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| R5F213J6ANNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F213J6CNNP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:RENESAS MCU |
| R5F213J6CNNP#U0 | 功能描述:MCU 1KB FLASH 32K ROM 36-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/3x/3JC 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測/復(fù)位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
| R5F213J6CNNP#W4 | 功能描述:MCU 32KB ROM 2.5KB RAM 36-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/3x/3JC 標(biāo)準(zhǔn)包裝:300 系列:78K0R/Ix3 核心處理器:78K/0R 芯體尺寸:16-位 速度:40MHz 連通性:3 線 SIO，I²C，LIN，UART/USART 外圍設(shè)備:DMA，LVD，POR，PWM，WDT 輸入/輸出數(shù):27 程序存儲器容量:16KB（16K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:38-SSOP 包裝:托盤 |
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