參數(shù)資料
型號(hào)： R5F213J5TNNP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, QCC40
封裝： 5 X 5 MM, 0.40 MM PITCH, QFN-40
文件頁(yè)數(shù)： 24/45頁(yè)
文件大?。?/td> 440K
代理商： R5F213J5TNNP
MSM6222B-01
Semiconductor
30/45
FEDL6222B-01-01
Generate biases externally and input them to the MSM6222B-01 (VDD, V1, V2, V3, V4,
and V5).
When the number of biases is 4, input the same potential to V2 and V3. The execution
time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(7) CG RAM address setting
L
R/W
Instruction code
L
RS
L
DB7
H
DB6
C5
DB5
C4
DB4
C3
DB3
C2
DB2
C1
DB1
C0
DB0
L
R/W
Instruction code
H
RS
E7
DB7
E6
DB6
E5
DB5
E4
DB4
E3
DB3
E2
DB2
E1
DB1
E0
DB0
L
R/W
Instruction code
L
RS
H
DB7
D6
DB6
D5
DB5
D4
DB4
D3
DB3
D2
DB2
D1
DB1
D0
DB0
When CG RAM addresses, bits C5 to C0 (binary), are set, the CG RAM is specified, until
the DD RAM address is set.
Write/read of the character pattern to and from the CPU begins with addresses, bits C5
to C0, starting from CG RAM selection.
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(8) DD RAM address setting
When the DD RAM addresses D6 to D0 (binary) are selected, the DD RAM is specified
until the DD RAM address is set.
Write/read of the character code to and from the CPU begins with addresses D6 to D0
starting from DD RAM selection.
In the 1-line display mode (N = H), however, D6 to D0 (binary) must be set to one of the
values among "00" to "4F" (hex.).
Likewise, in the 2-line mode, D6 to D0 (binary) must be set to one of the values among
"00" to "27" (hex.) or "40" to "67" (hex.).
When any value other than the above is input, it is impossible to make a normal write/
read of character codes to and from the DD RAM.
The execution time, when the OSC oscillation frequency is 250 kHz, is 40 ms.
(9) DD RAM and CG RAM data write
When E7 to E0 (binary) codes are written to the DD RAM or CG RAM, the cursor and
display move as described in "(5) Cursor and display shift". The execution time, when
the OSC oscillation frequency is 250 kHz, is 40 ms.
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