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參數(shù)資料
| 型號： | QL6250E-8PQ208I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PQFP208 |
| 封裝： | 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 63/64頁 |
| 文件大?。?/td> | 850K |
| 代理商： | QL6250E-8PQ208I |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
8
PLL Signals
Table 6 summarizes the key signals in QuickLogic PLLs.
NOTE: Because PLLCLK_IN and PLL_RESET signals have PLL_INPAD, and PLLPAD_OUT has OUTPAD,
you do not need to add additional pads to your design.
I/O Cell Structure
Eclipse-E features a variety of distinct I/O pins to maximize performance, functionality, and flexibility with
bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and
comply with the specific I/O standard selected. For single ended I/O standards, VCCIO specifies the input
tolerance and the output drive. For voltage referenced I/O standards (e.g SSTL), the voltage supplied to the
INREF pins in each bank specifies the input switch point. For example, the VCCIO pins must be tied to a 3.3 V
supply to provide 3.3 V compliance. Eclipse-E can also support the LVDS and LVPECL I/O standards with
the use of external resistors (see Table 7).
Table 6: QuickLogic PLL Signals
Signal Name
Description
PLLCLK_IN
Input clock signal.
PLL_RESET
Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset
to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work.
ONn_OFFCHIP
This is a reserved signal. It can be connected to VCC or GND.
CLKNET_OUT
Out to internal gates This signal bypasses the PLL logic before driving the clock tree. Note that
this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT).
PLLCLK_OUT
Out from PLL to internal gates This signal can drive the clock tree after going through the PLL.
PLLPAD_OUT
Out to off-chip This outgoing signal is used off-chip. The PLLPAD_OUT is always active, driving
the PLL-derived clock signal out through the pad. The PLLPAD_OUT will not oscillate if
PLL_RESET is asserted, or if the PLL is powered down.
LOCK_DETECT
Active High Lock detection signal
NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can
take a maximum of 200 clock cycles to sync with the input clock upon release of the PLL_RESET
signal.
Table 7: I/O Standards and Applications
I/O Standard
Reference Voltage
Output Voltage
Application
LVTTL
n/a
3.3 V
General Purpose
LVCMOS25
n/a
2.5 V
General Purpose
LVCMOS18
n/a
1.8 V
General Purpose
PCI
n/a
3.3 V
PCI Bus Applications
GTL+
1
n/a
Backplane
SSTL3
1.5
3.3 V
SDRAM
SSTL2
1.25
2.5 V
SDRAM
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