參數(shù)資料
型號： QL6250E-8PQ208I
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PQFP208
封裝： 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208
文件頁數(shù)： 38/64頁
文件大小： 850K
代理商： QL6250E-8PQ208I
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
43
VDED
I
No connect
This pin may be left unconnected. See pin VCCIO(C) for
more information.
VDED2
I
Voltage tolerance for JTAG pins
(TDI, TMS, TCK, and TRSTB)
These pins specify the input voltage tolerance for the JTAG
input pins. The legal range for VDED2 is between 1.71 V and
3.6 V. These do not specify output voltage of the JTAG
output, TDO. Refer to the VCCIO(C) pin section for
specifying the JTAG output voltage. VDED2 must be equal
to or greater than VCCIO(C).
VPUMP
I
Charge Pump Disable
This pin disables the internal charge pump for lower static
power consumption. To disable the charge pump, connect
VPUMP to 3.3 V. If the Disable Charge Pump feature is not
used, connect VPUMP to GND. For backwards compatibility
with Eclipse and EclipsePlus devices, connect VPUMP to
GND.
Table 27: PLLOUT Pin Supply Voltage
PLLOUT
VCCIO
PLLOUT(0)
VCCIO(E)
PLLOUT(1)
VCCIO(B)
PLLOUT(2)
VCCIO(A)
PLLOUT(3)
VCCIO(F)
Table 26: PT280 and PS484 Pin Descriptions (Continued)
Pin
Directio
n
Function
Description
相關(guān)PDF資料
PDF描述
QL6250E-8PQ208M FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PS484C FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-8PS484I FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-8PS484M FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6325-4PB516C FPGA, 1536 CLBS, 320640 GATES, PBGA516
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