參數(shù)資料
型號(hào)： QL6250E-8PQ208I
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PQFP208
封裝： 28 X 28 MM, 3.35 MM HEIGHT, MS-028, PLASTIC, QFP-208
文件頁(yè)數(shù)： 18/64頁(yè)
文件大?。?/td> 850K
代理商： QL6250E-8PQ208I
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
25
AC Characteristics*
*At VCC = 2.5 V, TA = 25°C, Worst Case Corner, Speed Grade = -6 (K = 1.01).
The AC Specifications are provided from Table 14 to Table 23. Logic cell diagrams and waveforms are
provided from Figure 25 to Figure 38.
Figure 25: Eclipse-E Logic Cell
Table 14: Logic Cell Delays
Symbol
Parameter
Value
Min
Max
t
PD
Combinatorial Delay of the longest path: time taken by the combinatorial circuit
to output
0.28 ns
0.98 ns
tSU
Setup time: time the synchronous input of the flip-flop must be stable before the
active clock edge
0.10 ns
0.25 ns
tHL
Hold time: time the synchronous input of the flip-flop must be stable after the
active clock edge
0 ns
t
CO
Clock-to-out delay: the amount of time taken by the flip-flop to output after the
active clock edge.
0.22 ns
0.52 ns
tCWHI
Clock High Time: required minimum time the clock stays high
0.46 ns
t
CWLO
Clock Low Time: required minimum time that the clock stays low
0.46 ns
tSET
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
0.69 ns
t
RESET
Reset Delay: time between when the flip-flop is ”reset” (low) and when the
output is consequently “reset” (low)
1.09 ns
tSW
Set Width: time that the SET signal must remain high/low
0.3 ns
tRW
Reset Width: time that the RESET signal must remain high/low
0.3 ns
相關(guān)PDF資料
PDF描述
QL6250E-8PQ208M FPGA, 960 CLBS, 248160 GATES, PQFP208
QL6250E-8PS484C FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-8PS484I FPGA, 960 CLBS, 248160 GATES, PBGA484
QL6250E-8PS484M FPGA, 960 CLBS, 248160 GATES, PBGA484
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