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參數(shù)資料
| 型號： | PXA255 |
| 廠商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255處理器 |
| 文件頁數(shù)： | 31/40頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | PXA255 |
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Electrical Specifications
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
31
Note:
If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times
indicated in
Figure 3
and nRESET timing requirements indicated in
Table 15
.
Figure 3. Power-On Reset Timing
Table 15. Power-On Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tR_VCCQ
VCCQ rise / stabilization time
0.01
—
100
ms
tR_VCCN
VCCN rise / stabilization time
0.01
—
100
ms
tR_VCC
VCC, PLL_VCC rise / stabilization time
0.01
—
10
ms
tD_VCCN
Delay between VCCQ applied and
VCCN applied
0
—
—
ms
tD_VCC
Delay from VCCN applied and VCC,
PLL_VCC applied
-10
—
—
ms
tD_NTRST
Delay between VCC, PLL_VCC stable
and nTRST de-asserted
10
—
—
ms
tD_JTAG
Delay between nTRST de-asserted and
JTAG pins active, with nRESET
asserted
0.03
—
—
ms
tD_NRESET
Delay between VCC, PLL_VCC stable
and nRESET de-asserted
10
—
—
ms
tD_OUT
Delay between nRESET de-asserted
and nRESET_OUT de--asserted
18.1
—
18.2
ms
tD_NCS0
Delay between nRESET_OUT
deasserted and nCS0 asserted
400
—
420
ns
VCCQ, PWR_EN
VCC
nTRST
JTAG PINS
nRESET
nRESET_OUT
NOTES:
1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the
processor enters sleep mode.
2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The
use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system’s
power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being
asserted.
t
R_VCCQ
t
R_VCC
t
D_NTRST
t
D_JTAG
t
D_NRESET
t
D_OUT
VCCN
t
R_VCCN
t
D_VCC
t
D_VCCN
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