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參數(shù)資料
| 型號： | PXA255 |
| 廠商： | Intel Corp. |
| 英文描述： | PXA255 Processor |
| 中文描述： | PXA255處理器 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | PXA255 |
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Electrical Specifications
30
Intel PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Note:
The minimum duty cycle for an external signal driven into PEXTAL is 40/60.
4.7
Reset and Power AC Timing Specifications
The processor asserts the nRESET_OUT pin in one of several different modes:
Power on
Hardware reset
Watchdog reset
GPIO reset
Sleep mode
The following sections provide the timing and specifications for the entry and exit of these modes.
4.7.1
Power-On Timing
The external voltage regulator and other power-on devices must provide the processor with a
specific sequence of power and resets to ensure proper operation.
Figure 3, “Power-On Reset
Timing” on page 31
, shows this sequence and is detailed in
Table 15, “Power-On Timing
Specifications” on page 31
.
On the processor, it is important that the power supplies be powered up in a certain order to avoid
high current situations. The required order is:
1. VCCQ
2. VCCN
3. VCC and PLL_VCC
On the processor, it is important that the VCCQ power supply be powered up before or at the same
time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up
anytime within the specification shown in
Figure 3
and
Table 15
.
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