參數(shù)資料
型號: PUMA2F16006MB-120E
元件分類: PROM
英文描述: 512K X 32 FLASH 5V PROM MODULE, 120 ns, CHMA66
封裝: CERAMIC, PGA-66
文件頁數(shù): 7/26頁
文件大?。?/td> 258K
代理商: PUMA2F16006MB-120E
Issue 5.1 May 2001
PAGE 15
Note that the Program command cannot change a bit set at ’0’ back to
’1’ and attempting to do so will cause an error. One of the Erase
Commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
Unlock Bypass Command
The Unlock Bypass command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access
time to the device is long (as with some EPROM programmers)
considerable time saving can be made by using these commands. Three
Bus Write operations are required to issue the Unlock Bypass
command.
Once the Unlock Bypass command has been issued the memory will
only accept the Unlock By-pass Program command and the Unlock
Bypass Reset command. The memory can be read as if in Read mode.
Unlock Bypass Program Command
The Unlock Bypass Program command can be used to program one
address in memory at a time. The command requires two Bus Write
operations, the final write operation latches the address and data in the
internal state machine and starts the Program/Erase Controller. The
Program operation using the Unlock Bypass Program command
behaves identically to the Program operation using the Program
command. A protected block cannot be programmed; the operation
cannot be aborted and the Status Register is read. Errors must be reset
using the Read/Reset command, which leaves the device in Unlock By-
pass Mode. See the Program command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used to return to Read/
Reset mode from Unlock Bypass Mode. Two Bus Write operations are
required to issue the Unlock Bypass Reset command.
Chip Erase Command
The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip Erase Command and
start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks
are erased. If all of the blocks are protected the Chip Erase operation
appears to start but will terminate within about 100
s, leaving the data
unchanged. No error condition is given when protected blocks are
ignored. During the erase operation the memory will ignore all
commands. It is not possible to issue any command to abort the
operation. Typical chip erase times are given in Table 5. All Bus Read
operations during the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status
Register for more details.
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