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參數(shù)資料
| 型號(hào)： | PUMA2F16006MB-120E |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 5V PROM MODULE, 120 ns, CHMA66 |
| 封裝： | CERAMIC, PGA-66 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 258K |
| 代理商： | PUMA2F16006MB-120E |
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Status
Register
Issue 5.1 May 2001
PAGE 18
Bus Read operations from any address always read the Status Register
during Program and Erase operations. It is also read during Erase
Suspend when an address within a block being erased is accessed. The
bits in the Status Register are summarized in Table 3, Status Register
Bits.
Data Polling Bit (D7)
The Data Polling Bit can be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has
responded to an Erase Suspend. The Data Polling Bit is output on D7
when the Status Register is read.
During Program operations the Data Polling Bit outputs the complement
of the bit being programmed to D7. After successful completion of the
Program operation the memory returns to Read mode and Bus Read
operations from the address just programmed output D7, not its
complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement
of the erased state of D7. After successful completion of the Erase
operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus
Read operation within a block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase Controller has
suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the
Data Polling Bit. A Valid Address is the address being programmed or
an address within the block being erased.
Toggle Bit (D6)
The Toggle Bit can be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has
responded to an Erase Suspend. The Toggle Bit is output on D6 when
the Status Register is read.
During Program and Erase operations the Toggle Bit changes from ’0’
to ’1’ to ’0’, etc., with successive Bus Read operations at any address.
After successful completion of the operation the memory returns to Read
mode.
During Erase Suspend mode the Toggle Bit will output when addressing
a cell within a block being erased. The Toggle Bit will stop toggling when
the Program/Erase Controller has suspended the Erase operation.
Figure 5, Data Toggle Flowchart, gives an example of how to use the
Data Toggle Bit.
Error Bit (D5)
The Error Bit can be used to identify errors detected by the Program/
Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase
or Chip Erase operation fails to write the correct data to the memory. If
the Error Bit is set a Read/Reset command must be issued before other
commands are issued. The Error bit is output on D5 when the Status
Register is read.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PUMA2F16006MB-12E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|512KX32|HYBRID|PGA|66PIN|CERAMIC |
| PUMA2F16006MB-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Flash EEPROM Module |
| PUMA2F16006MB-15E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Flash EEPROM Module |
| PUMA2F16006MB-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA2F16006MB-70E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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