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參數(shù)資料
| 型號： | PUMA2F16006MB-120E |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 5V PROM MODULE, 120 ns, CHMA66 |
| 封裝： | CERAMIC, PGA-66 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 258K |
| 代理商： | PUMA2F16006MB-120E |
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Device
Bus
Operations
Issue 5.1 May 2001
PAGE 12
There are five standard bus operations that control the device. These are
Bus Read, Bus Write, Output Disable, Standby and Automatic Standby.
See Table 2, Bus Operations, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ignored by the memory and
do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers
in the Command Interface. A valid Bus Read operation involves setting
the desired address on the Address Inputs, applying a Low signal, V
IL,
to Chip Enable and Output Enable and keeping Write Enable High, V
IH.
The Data Inputs/Outputs will output the value, see Figure 1, Read Mode
AC Waveforms, and Read AC Characteristics, for details of when the
output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write
operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling
edge of Chip Enable or Write Enable, whichever occurs last. The Data
Inputs/Outputs are latched by the Command Interface on the rising edge
of Chip Enable or Write Enable, whichever occurs first. Output Enable
must remain High, V
IH, during the whole Bus Write operation. See
Figures 2 and 3, Write AC Waveforms, and Write AC Characteristics, for
details of the timing requirements.
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output
Enable is High, V
IH.
Standby
When Chip Enable is High, V
IH, the Data Inputs/Outputs pins are placed
in the high impedance state and the Supply Current is reduced to the
Standby level. When Chip Enable is at V
IH the Supply Current is reduced
to the TTL Standby Supply Current, I
SB1. For Standby current levels see
DC Characteristics. During program or erase operations the memory will
continue to use the Program/Erase Supply Current, I
CCP, for Program or
Erase operations until the operation completes.
Special Bus Operations
Additional bus operations can be performed to read the Electronic
Signature and also to apply and remove Block Protection. These bus
operations are intended for use by programming equipment and are not
usually used in applications. They require V
ID to be applied to some pins.
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| PUMA2F16006MB-12E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|512KX32|HYBRID|PGA|66PIN|CERAMIC |
| PUMA2F16006MB-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Flash EEPROM Module |
| PUMA2F16006MB-15E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 Flash EEPROM Module |
| PUMA2F16006MB-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| PUMA2F16006MB-70E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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