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參數(shù)資料
| 型號： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
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Data Sheet
PT7D5820/5820L Large Digital Switch
6
PT0098(12/03)
Ver:1
Pin No.
Name
Type
Description
84-PL-
CC
100-M-
QFP
40
13
WFPS
I
Wide Frame Pulse Select: When 1, enables the WFP Frame Alignment interface.
When 0, the device operates in ST-BUS/GCI mode.
41-48
14-21
A0-A7
I
Address 0 - 7: in non-multiplexed CPU bus operation, these lines provide the A0
- A7 address lines to the internal memories.
49
22
DS/RD
I
Data Strobe / Read: For Motorola multiplexed bus operation, this input is DS.
This active high DS input works in conjunction with CS to enable the read and
write operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active
low input works in conjunction with CS to enable the read and write operations.
For Intel multiplexed bus operation, this input is RD. This active low input sets
the data bus lines (AD0-AD7, D8-D15) as outputs.
50
23
R/W /
WR
I
Read/Write / Write: In the cases of Motorola non-multiplexed and multiplexed
bus operations, this input is R/W. This input controls the direction of the data bus
lines (AD0 - AD7, D8-D15) during a microprocessor access.
For Intel multiplexed bus operation, this input is WR. This active low input is
used with CS to control the data bus (AD0 - 7, D8 - D15) lines as inputs.
51
24
CS
I
Chip Select: Active low input used by a processor to activate the microprocessor
port of MLDS.
52
25
AS/AL-
E
I
Address Strobe or Latch Enable: This input is used if multiplexed bus operation
is selected via the IM input pin. For Motorola non-multiplexed bus operation,
connect this pin to ground. This pin is pulled low by an internal pull-down when
not driven.
53
26
IM
I
CPU Interface Mode: When IM is high, the microprocessor port is in the
multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed
mode. This pin is pulled low by an internal pull-down when not driven.
55-62
32-39
AD0-7
I/O
Address/Data Bus 0 to 7: These pins are the eight least significant data bits of the
microprocessor port. In multiplexed mode, these pins are also the input address
bits of the microprocessor port.
65-72
42-49
D8-15
I/O
Data Bus 8-15: These pins are the eight most significant data bits of the
microprocessor port.
73
50
DTA
O
Data Transfer Acknowledgement: Indicates that a data bus transfer is complete.
When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for
faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to
hold a HIGH level when the pin is tri-stated.
74
55
CSTo
O
Control Output: This is a 4.096, 8.192 or 16.384Mb/s output containing 512, 1024
or 2048 bits per frame respectively. The level of each bit is determined by the
CSTo bit in the connection memory. See External Drive Control Section.
76
57
ODE
I
Output Drive Enable: This is the output enable control for the STo0 to STo15
serial outputs. When ODE input is low and the OSB bit of the IMS register is
low, STo0-15 are in a high impedance state. If this input is high, the STo0-15
output drivers are enabled. However, each channel may still be put into a high
impedance state by using the per channel control bit in the connection memory.
-
1-4
27-30
51-54
77-80
NC
-
No connection
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