![](http://datasheet.mmic.net.cn/260000/PT7D5820_datasheet_15959089/PT7D5820_21.png)
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Data Sheet
PT7D5820/5820L Large Digital Switch
21
PT0098(12/03)
Ver:1
Frame Input Offset Register 0, 1, 2, 3 (FOR0, 1, 2, 3), Read/Write
-- Address: 03H, 04H, 05H, 06H, Value after reset: 0000H for all FOR register
FOR0 register
15
FOR1 register
FOR2 register
FOR3 register
* n denotes an input stream number from 0 to 15.
0
OF32
OF31
OF30
BBM3
OF22
OF21
OF20
BBM2
OF12
OF11
OF10
BBM1
OF02
OF01
OF00
BBM0
15
0
OF72
OF71
OF70
BBM7
OF62
OF61
OF60
BBM6
OF52
OF51
OF50
BBM5
OF42
OF41
OF40
BBM4
15
0
OF112 OF111 OF110 BBM11 OF102 OF101 OF100 BBM10 OF92
OF91
OF90
BBM9
OF82
OF81
OF80
BBM8
15
0
OF152 OF151 OF150 BBM15 OF142 OF141 OF140 BBM14 OF132 OF131 OF130 BBM13 OF122 OF121 OF120 BBM12
Name*
Description
OFn2, OFn1, OFn0
Offset Bits 2,1 & 0.
These three bits define how long the serial interface receiver takes to
recognize and store bit 0 from the STi input pin: i.e., to start a new frame. The input frame offset
can be selected to +2 bit cell periods from the point where the external frame pulse input signal is
applied to the F0i input of the device. See Figure 10 & Table 9.
BBMn
Bit Boundary Mark.
ST-BUS mode: BBMn =0, The boundary of bit7 channel 0 is at the first
falling edge of the master clock after the falling edge of the frame pulse. BBMn =1, The boundary
of bit7 channel 0 is 1/4 bit cell width later that the boundary when the BBMn = 0.
GCI mode: BBMn =0, The boundary of bit7 channel 0 is half cycle before the first falling edge of
the master clock after the rising edge of the frame pulse. BBMn =1, The boundary of bit7 channel
0 is 1/4 bit cell width later that the boundary when the BBMn = 0.