- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368349 > PT7D5820 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package PDF資料下載
參數(shù)資料
| 型號： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Data Sheet
PT7D5820/5820L Large Digital Switch
13
PT0098(12/03)
Ver:1
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all switching
configurations by making use of a multiple data memory buffer.
Input channel data is written into the data memory buffers
during frame n will be read out during frame n+2.
In the PT7D5820/5820L, the minimum throughput delay achiev-
able in the constant delay mode will be one frame. For example,
in 2 Mb/s mode, when input time-slot 31 is switched to output
time-slot 0. The maximum delay of 94 time-slots of delay oc-
curs when time-slot 0 in a frame is switched to time-slot 31 in
the frame. See Table 3.
Microprocessor Interface
The PT7D5820/5820L provides a parallel microprocessor inter-
face for non-multiplexed or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed and Intel
or Motorola multiplexed buses.
If the IM pin is low, the PT7D5820/5820L microprocessor inter-
face assumes Motorola non-multiplexed bus mode. If the IM
pin is high, the device microprocessor interface accepts two
different timing modes (Intel and Motorola) which allow direct
connection to multiplexed microprocessors.
The microprocessor interface automatically identifies the type
of microprocessor bus connected to the PT7D5820/5820L. This
circuit uses the level of the DS/RD input pin at the rising edge
of AS/ALE to identify the appropriate bus timing connected to
the PT7D5820/5820L. If DS/RD is low at the rising edge of AS/
ALE, then the Intel multiplexed timing is selected. If DS/RD is
high at the rising edge of AS/ALE, then the Motorola multi-
plexed bus timing is selected.
For multiplexed operation, the required signals are the 8-bit
data and address (AD0-AD7), 8-bit Data (D8-D15), Address
strobe/Address latch enable (AS/ALE), Data strobe/Read (DS/
RD), Read/Write /Write (R/W /WR), Chip select (CS) and Data
transfer acknowledge (DTA). See
Figure 10
and
Figure 11
for
multiplexed parallel microport timing.
For the Motorola non-multiplexed bus, the required signals
are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus
(A0-A7) and 4 control lines (CS, DS, R/W and DTA). See
Fig-
ure 12
for Motorola non-multiplexed microport timing. The
PT7D5820/5820L microport provides access to the internal reg-
isters, connection and data memories. All locations provide
read/write access except for the data memory and the frame
alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the
internal registers and memories of the PT7D5820/5820L. If the
A7 address input is low, then the control (CR), interface mode
selection (IMS), frame alignment (FAR) and frame input offset
(FOR) registers are addressed by A6 to A0 according to
Table
4
.
If the A7 is high, then the remaining address input lines are
used to select memory subsections of up to 128 locations cor-
responding to the maximum number of channels per input or
output stream. The address input lines and the stream address
bits (STA) of the control register allow access to the entire data
and connection memories.
The control and IMS registers together control all the major
functions of the device. The IMS register should be pro-
grammed immediately after system power-up to establish the
desired switching configuration as explained in the Serial Data
Interface Timing and Switching Configurations sections.
Table 2. Variable Throughput Delay Value
Input Rate
Delay for Variable Throughput Delay Mode
(m - output channel number, n - input channel number)
m < n
m= n, n+1, n+2
32-(n-m) time-slots
m-n+32 time-slots
64-(n-m) time-slots
m-n+64 time-slots
128-(n-m) time-slots
m-n+128 time-slots
m> n+2
m-n time-slots
m-n time-slots
m-n time-slots
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Table 3. Constant Throughput Delay Value
Input Rate
Delay for Constant Throughput Delay Mode
(m - output channel number, n - input channel number)
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m - 1) time-slots
128 + (128 - n) + (m - 1) time-slots
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PT7D6555 | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| PT7M7803RT | μP Supervisor Circuits? |
| PT7V2727 | 3.3v/5.0v operating voltage |
| PT7V2727W | 3.3v/5.0v operating voltage |
| PT7V3727W | 3.3v/5.0v operating voltage |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PT7FFSDGY | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, GY |
| PT7FFSDI | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, IV |
| PT7FSD | 制造商:Hubbell Wiring Device-Kellems 功能描述:THRU-FLOOR FITTING, 3 FLUSH FRPT |
| PT7FSDBLA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BK |
| PT7FSDBRA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。