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參數(shù)資料
| 型號： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 19/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
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Data Sheet
PT7D5820/5820L Large Digital Switch
19
PT0098(12/03)
Ver:1
Table 8. Serial Data Rate Selection (16 input x 16 output)
Interface Mode Selection Register (IMS), Read/Write
-- Address: 01H, Value after reset: 0000H
15
0
0
0
0
0
0
0
BPD4 BPD3 BPD2 BPD1 BPD0
BPE
OSB
SFE
DR1
DR0
Bit
Name
Description
15 - 10
9-5
Unused
BPD4 - 0
Must be zero for normal operation.
Block Programming Data.
These bits carry the value to be loaded into the connection memory
block whenever the memory block programming feature is activated. After the MBP bit in the control
register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4- 0 are loaded into bit 15
to bit 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0.
4
BPE
Begin Block programming Enable.
A zero to one transition of this bit enables the memory block
programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same
write operation. Once the BPE bit is set high, the device requires two frames to complete the block
programming. After the programming function has finished, the BPE bit returns to zero to indicate
the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the
programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure
proper operation.
3
OSB
Output Stand By.
When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in high
impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0 to STo15 function
normally. When ODE = 1, STo0 to STo15 output drivers function normally.
2
SFE
Start Frame Evaluation.
A zero to one transition in this bit starts the frame evaluation procedure.
When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To
start another frame evaluation cycle, set this bit to zero for at least one frame.
Data Rate Select.
Input / Output data rate selection. See
Table 8
or detailed programming.
1-0
DR1 - 0
DR1
0
0
1
1
DR0
0
1
0
1
Data Rate Selected
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
Master Clock Required
4.096 MH
8.192 MHz
16.384 MHz
Reserved
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