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參數(shù)資料
| 型號： | PT7D5820 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2Pak package |
| 中文描述： | 大型數(shù)字開關(guān)？ |
| 文件頁數(shù)： | 20/39頁 |
| 文件大?。?/td> | 530K |
| 代理商： | PT7D5820 |
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Data Sheet
PT7D5820/5820L Large Digital Switch
20
PT0098(12/03)
Ver:1
Frame Alignment Register (FAR), Read
-- Address: 02H, Value after reset: 0000H
Figure 8. Example for Frame Alignment Measurement
15
0
0
0
0
CFE
FD11 FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
15 - 13
12
Unused
CFE
Must be zero for normal operation.
Complete Frame Evaluation.
When CFE = 1, the frame evaluation is completed and bits FD10 to
FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the
IMS register is changed from 1 to 0.
11
FD11
Frame Delay Bit 11.
The falling edge of FE (or rising edge for GCI mode) is sampled during the
CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the
measurement resolution to 1/2 CLK cycle.
10-0
FD10 - 0
Frame Delay Bits.
The binary value expressed in these bits refers to the measured input offset
value. These bits are reset to zero when the SFE bit of the IMS register changes from 1 to 0.
(FD10 = MSB, FD0 = LSB)
0
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] =09
)
(FD11=1, sample at CLK high phase)
0
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
ST-BUS Frame
CLK
Offset Value
FE Input
(FD[10:0] =06
)
(FD11=0, sample at CLK low phase)
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相關(guān)代理商/技術(shù)參數(shù) |
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| PT7FFSDGY | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, GY |
| PT7FFSDI | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, 1 SERV, FURN FEED, IV |
| PT7FSD | 制造商:Hubbell Wiring Device-Kellems 功能描述:THRU-FLOOR FITTING, 3 FLUSH FRPT |
| PT7FSDBLA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BK |
| PT7FSDBRA | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLUSH FRPT, W/20A DUP/TELE/DATA,BR |
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